AN 846: Intel® Stratix® 10 Forward Error Correction

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ID 683805
Date 7/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Necessity of Error Correction 3. FEC Selection 4. FEC in Intel® Stratix® 10 H-Tile Devices 5. FEC in Intel® Stratix® 10 E-Tile Devices 6. FEC Implementation Using the E-Tile Channel Placement Tool 7. FEC in Practical Application 8. Hardware Results 9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
2. Necessity of Error Correction x
2.1. Solutions to Transmission Errors 2.2. Error Correction Codes 2.3. What is FEC?
2.1. Solutions to Transmission Errors x
2.1.1. Parity and Cyclic Redundancy Check 2.1.2. Error Correction Code (ECC) Block Coding
2.3. What is FEC? x
2.3.1. FEC Definitions
3. FEC Selection x
3.1. Key Considerations when Choosing a FEC
4. FEC in Intel® Stratix® 10 H-Tile Devices x
4.1. Fire Code (802.3ap, 10GBASE-KR)
4.1. Fire Code (802.3ap, 10GBASE-KR) x
4.1.1. FEC Block Format 4.1.2. FEC Block Composition 4.1.3. FEC Sublayer for BASE-R PHYs 4.1.4. L-Tile/H-Tile Implementation
4.1.4. L-Tile/H-Tile Implementation x
4.1.4.1. Transcode Encoder 4.1.4.2. KR FEC Encoder 4.1.4.3. KR FEC Scrambler 4.1.4.4. KR FEC TX Gearbox 4.1.4.5. KR FEC RX Gearbox 4.1.4.6. Transcode Decoder
5. FEC in Intel® Stratix® 10 E-Tile Devices x
5.1. Types of RS-FEC 5.2. 100GBASE-KR4 5.3. 100GBASE-KP4 5.4. FEC Decoders 5.5. Specifications 5.6. Functions Within the RS-FEC Sublayer
5.1. Types of RS-FEC x
5.1.1. RS (528, 514, t = 7, m = 10) 5.1.2. RS (544, 514, t = 15, m = 10) 5.1.3. Supported RS-FEC Modes in E-Tile Devices
5.2. 100GBASE-KR4 x
5.2.1. 100GBASE-KR4 Mapping (IEEE802.3bj Clause 91)
5.3. 100GBASE-KP4 x
5.3.1. 100GBASE-KP4 Mapping (IEEE802.3bj Clause 91)
5.6. Functions Within the RS-FEC Sublayer x
5.6.1. Lane Block Synchronization 5.6.2. Alignment Lock and Deskew 5.6.3. Lane Re-order 5.6.4. Alignment Marker Removal 5.6.5. 64B/66B to 256B/257B Transcoder
7. FEC in Practical Application x
7.1. Datacenter Applications Scenario
8. Hardware Results x
8.1. Test Design 8.2. Test Setup 8.3. Insertion Loss Plots 8.4. FEC Statistics Tool 8.5. Hardware Data 8.6. Comparison to the Specification 8.7. References
1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction

4.1.1. FEC Block Format

The length of the FEC block is 2112 bits. Each FEC block contains 32 rows of 65 bits each; 64 bits of payload and 1-bit transcoding overhead (T bits).

At the end of each block there is 32-bit overhead or parity check bits. Transmission is from left to right within each row, and from top to bottom between rows. The payload bits carry the information symbols from the PCS layer.

Table 4.  FEC Block Format
T0 64-bit payload Word 0 T1 64-bit payload Word 1 T2 64-bit payload Word 2 T3 64-bit payload Word 3
T4 64-bit payload Word 4 T5 64-bit payload Word 5 T6 64-bit payload Word 6 T7 64-bit payload Word 7
T8 64-bit payload Word 8 T9 64-bit payload Word 9 T10 64-bit payload Word 10 T11 64-bit payload Word 11
T12 64-bit payload Word 12 T13 64-bit payload Word 13 T14 64-bit payload Word 14 T15 64-bit payload Word 15
T16 64-bit payload Word 16 T17 64-bit payload Word 17 T18 64-bit payload Word 18 T19 64-bit payload Word 19
T20 64-bit payload Word 20 T21 64-bit payload Word 21 T22 64-bit payload Word 22 T23 64-bit payload Word 23
T24 64-bit payload Word 24 T25 64-bit payload Word 25 T26 64-bit payload Word 26 T27 64-bit payload Word 27
T28 64-bit payload Word 28 T29 64-bit payload Word 29 T30 64-bit payload Word 30 T31 64-bit payload Word 31
32 parity bits            

Total FEC block length = (32 × 65) + 32 = 2112 bits.

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