AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683783
Date 7/26/2019
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1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.1. Tutorial Overview

This tutorial describes the core and root partition reuse flows for both the Developer and the Consumer roles. At a high level, the core and root partition reuse flows are similar. Both flows preserve and reuse a design partition as a .qdb file. The Developer defines, compiles, and preserves the block in the Developer project, and the Consumer reuses the block, along with their own logic, in one or more Consumer projects.

Reusing Core Partitions

Core partition reuse allows a Developer to create, preserve, and export a partition for reuse. The Developer exports the core partition as a .qdb, and then a Consumer can reuse that core partition in another project. The core partition can include only core resources, such as LUTs, flip-flops, M20K memory, and DSP blocks. To use this flow you assign the .qdb to an instance in the Consumer project.

Figure 1. Core Partition Reuse Example

Reusing Root Partitions

Root partition reuse enables you to export a synthesized or final snapshot of the device periphery and associated core logic. To export and reuse periphery elements, you export the root partition. The periphery resources include all the hardened IP in the device periphery (such as general purpose I/O, PLLs, high-speed transceivers, PCIe, and external memory interfaces), as well as associated core logic. The Developer also reserves a region for core logic development by the Consumer. The Developer defines this reserved region with a partition. The Developer defines at least the module's port connections as a black box file.

Figure 2. Root Partition Reuse Example

When you export the synthesized or final partition as a .qdb, the .qdb preserves the results of that compilation stage. When you subsequently reuse that partition in another project, the Compiler reuses the previous compilation results from the .qdb for that partition, thereby leveraging the previous design efforts of the Developer.

The tutorial includes the following modules:

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