AN 839: Design Block Reuse Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683783
Date 7/26/2019
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Document Table of Contents x
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. AN 839: Design Block Reuse Tutorial Document Revision History
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. Step 4: Hardware Verification (Optional)
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 839: Design Block Reuse Tutorial for Intel® Arria® 10 FPGA Development Board

1.4.3. Step 3: Create the Black Box File

Integrating a core partition .qdb into another project requires that you add a supporting black box file to the Consumer project. The black box file defines the ports and port interface types for the block that you reuse in the Consumer project. Follow these steps to create a black box port definitions file for the blinking_led partition.
  1. To create a new text file, click File > New, select SystemVerilog HDL File under Design Files, and then click OK. Create a file that contains only the port definitions for the partition you export. These are the same port definitions that the blinking_led.sv file specifies: 
    module blinking_led (
    output [3:0] value,
    input      clock
    );

endmodule
  2. Save the black box file as blinking_led_bb.sv. When saving this file, disable the option to Add file to current project.
    Figure 9. Disable Add File to Current Project
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