External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.24. sideband16

address=79(32 bit)

Field Bit High Bit Low Description Access
mmr_3ds_refresh_ack 31 0 DDR4 3DS Refresh Acknowledge. When asserted, indicates acknowledgement for the DDR4 3DS refresh. Read
[7:0] Refresh acknowledgement for logical rank [7:0] for physical rank 0.
[15:8] Refresh acknowledgement for logical rank [7:0] for physical rank 1.
[23:16] Refresh acknowledgement for logical rank [7:0] for physical rank 2.
[31:24] Refresh acknowledgement for logical rank [7:0] for physical rank 3.