External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

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12.4.2. Latency

The following latency data applies to all memory protocols supported by the Intel® Stratix® 10 EMIF IP.

Table 348.  Latency in Full-Rate Memory Clock Cycles
Rate 1 Controller Address & Command PHY Address & Command Memory Read Latency 2 PHY Read Data Return Controller Read Data Return Round Trip Round Trip Without Memory
Half:Write 12 2 3-23
Half:Read 8 2 3-23 6 8 27-47 24
Quarter:Write 14 2 3-23
Quarter:Read 10 2 3-23 6 14 35-55 32
Half:Write (ECC) 14 2 3-23
Half:Read (ECC) 12 2 3-23 6 8 31-51 28
Quarter:Write (ECC) 14 2 3-23
Quarter:Read (ECC) 12 2 3-23 6 14 37-57 34
  1. User interface rate; the controller always operates in half rate.
  2. Minimum and maximum read latency range for DDR3 and DDR4.