AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

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ID 683700
Date 8/17/2020
Public
Document Table of Contents
Document Table of Contents x
1. Using ADI AD9217 with Intel Stratix 10 Devices
1. Using ADI AD9217 with Intel Stratix 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
1.3. Design Description x
1.3.1. Overall Design Flow 1.3.2. Low-Latency C2C Interface
1.3.2. Low-Latency C2C Interface x
1.3.2.1. Lane Mapping in C2C 1.3.2.2. C2C Design Flow 1.3.2.3. Calibration Operation Sequence 1.3.2.4. Calibration Operation Sequence Descriptions
1.5. Parameterization x
1.5.1. Design Parameters 1.5.2. Derived Parameters 1.5.3. Clocks
1.7. Simulation x
1.7.1. Procedure
1.8. Latency Measurement for 10G Design x
1.8.1. Latency Calculations
1.11. Appendix: 5G Design Example x
1.11.1. Hardware Setup 1.11.2. Parameterization 1.11.3. Directory Structure 1.11.4. Simulation 1.11.5. Hardware Testing 1.11.6. Latency Measurement for 5G Design
1.11.2. Parameterization x
1.11.2.1. Design Parameters 1.11.2.2. Derived Parameters 1.11.2.3. Clocks
1.11.4. Simulation x
1.11.4.1. Procedure
1.11.5. Hardware Testing x
1.11.5.1. Procedure
1.11.6. Latency Measurement for 5G Design x
1.11.6.1. Latency Calculations
1. Using ADI AD9217 with Intel Stratix 10 Devices

1.3.2.4. Calibration Operation Sequence Descriptions

  • Data capture start is given by the FPGA to initiate the calibration operation sequence.
  • During bit/clock alignment phase, the FPGA sets the alignment pattern and disables the scrambler. The same is done in ADC (AD9217) by configuring the registers 0x4B1 and 0x4A0 through SPI. Once the bit alignment is done in the FPGA, the word alignment phase starts.
  • During the word alignment phase, the FPGA sets the alignment pattern. In ADC (AD9217), configure the register 0x4A0 with appropriate bits to select word alignment pattern. Once the word alignment is done, the channel alignment starts in the FPGA.
  • During the channel alignment phase, the FPGA sets the alignment pattern. In ADC (AD9217), configure the register 0x4A0 with appropriate bits to select the channel alignment pattern. During this phase, the lane de-skew is taken care in the C2C module.
Figure 6. Channel Alignment in C2C
  • In Figure 6, Lane_0 and Lane_2 are aligned and its channel align count is 0. And in Lane_1 and Lane_n, there is a 32-bit delay in data. Therefore, the channel align count is 2.
  • Based on the channel align count, the channels are aligned properly.
  • After the lane/channel alignment is done and when the break pattern is detected, the scrambler is enabled in both FPGA and AD9217 and the ADC starts the data transmission.
  • The FPGA starts capturing the ADC data and monitors the parity bit.
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