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1. Datasheet
2. Quick Start Guide
3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet
1.2. Release Information
1.3. Device Family Support
1.4. Configurations
1.5. Debug Features
1.6. IP Core Verification
1.7. Resource Utilization
1.8. Recommended Speed Grades
1.9. Creating a Design for PCI Express
3.1. Parameters
3.2. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Settings
3.3. Base Address Register (BAR) and Expansion ROM Settings
3.4. Base and Limit Registers for Root Ports
3.5. Device Identification Registers
3.6. PCI Express and PCI Capabilities Parameters
3.7. Vendor Specific Extended Capability (VSEC)
3.8. Configuration, Debug, and Extension Options
3.9. PHY Characteristics
3.10. Example Designs
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices
4.2. Hard IP Block Placement In Intel® Arria® 10 Devices
4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate
4.5. PCI Express Gen3 Bank Usage Restrictions
5.1. Clock Signals
5.2. Reset, Status, and Link Training Signals
5.3. ECRC Forwarding
5.4. Error Signals
5.5. Interrupts for Endpoints
5.6. Interrupts for Root Ports
5.7. Completion Side Band Signals
5.8. Parity Signals
5.9. LMI Signals
5.10. Transaction Layer Configuration Space Signals
5.11. Hard IP Reconfiguration Interface
5.12. Power Management Signals
5.13. Physical Layer Interface Signals
15.4.1. ebfm_barwr Procedure
15.4.2. ebfm_barwr_imm Procedure
15.4.3. ebfm_barrd_wait Procedure
15.4.4. ebfm_barrd_nowt Procedure
15.4.5. ebfm_cfgwr_imm_wait Procedure
15.4.6. ebfm_cfgwr_imm_nowt Procedure
15.4.7. ebfm_cfgrd_wait Procedure
15.4.8. ebfm_cfgrd_nowt Procedure
15.4.9. BFM Configuration Procedures
15.4.10. BFM Shared Memory Access Procedures
15.4.11. BFM Log and Message Procedures
15.4.12. Verilog HDL Formatting Functions
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9.1.5. Interrupts
The Hard IP for PCI Express offers the following interrupt mechanisms:
- Message Signaled Interrupts (MSI)— MSI uses the TLP single dword memory writes to to implement interrupts. This interrupt mechanism conserves pins because it does not use separate wires for interrupts. In addition, the single dword provides flexibility in data presented in the interrupt message. The MSI Capability structure is stored in the Configuration Space and is programmed using Configuration Space accesses.
- MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. The MSI-X Capability structure points to an MSI-X table structure and MSI-X PBA structure which are stored in memory. This scheme is in contrast to the MSI capability structure, which contains all of the control and status information for the interrupt vectors.
- Legacy interrupts—The app_int_sts port controls legacy interrupt generation. When app_int_sts is asserted, the Hard IP generates an Assert_INT<n> message TLP.