Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

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ID 683647
Date 6/03/2021
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Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Quick Start Guide 3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings 4. Physical Layout 5. Interfaces and Signal Descriptions 6. Registers 7. Interrupts 8. Error Handling 9. PCI Express Protocol Stack 10. Transaction Layer Protocol (TLP) Details 11. Throughput Optimization 12. Design Implementation 13. Additional Features 14. Hard IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Transaction Layer Packet (TLP) Header Formats B. Lane Initialization and Reversal C. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive D. Document Revision History
1. Datasheet x
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Debug Features 1.6. IP Core Verification 1.7. Resource Utilization 1.8. Recommended Speed Grades 1.9. Creating a Design for PCI Express
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet x
1.1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Features
1.6. IP Core Verification x
1.6.1. Compatibility Testing Environment
2. Quick Start Guide x
2.1. Directory Structure 2.2. Design Components 2.3. Generating the Design 2.4. Simulating the Design 2.5. Compiling and Testing the Design in Hardware
3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings x
3.1. Parameters 3.2. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Settings 3.3. Base Address Register (BAR) and Expansion ROM Settings 3.4. Base and Limit Registers for Root Ports 3.5. Device Identification Registers 3.6. PCI Express and PCI Capabilities Parameters 3.7. Vendor Specific Extended Capability (VSEC) 3.8. Configuration, Debug, and Extension Options 3.9. PHY Characteristics 3.10. Example Designs
3.6. PCI Express and PCI Capabilities Parameters x
3.6.1. PCI Express and PCI Capabilities 3.6.2. Error Reporting 3.6.3. Link Capabilities 3.6.4. MSI and MSI-X Capabilities 3.6.5. Slot Capabilities 3.6.6. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Intel® Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions x
5.1. Clock Signals 5.2. Reset, Status, and Link Training Signals 5.3. ECRC Forwarding 5.4. Error Signals 5.5. Interrupts for Endpoints 5.6. Interrupts for Root Ports 5.7. Completion Side Band Signals 5.8. Parity Signals 5.9. LMI Signals 5.10. Transaction Layer Configuration Space Signals 5.11. Hard IP Reconfiguration Interface 5.12. Power Management Signals 5.13. Physical Layer Interface Signals
5.10. Transaction Layer Configuration Space Signals x
5.10.1. Configuration Space Register Access Timing 5.10.2. Configuration Space Register Access
5.13. Physical Layer Interface Signals x
5.13.1. Serial Data Signals 5.13.2. PIPE Interface Signals 5.13.3. Test Signals 5.13.4. Intel® Arria® 10 Development Kit Conduit Interface
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. Advanced Error Reporting Capability
6.5. Intel-Defined VSEC Registers x
6.5.1. CvP Registers
6.6. Advanced Error Reporting Capability x
6.6.1. Uncorrectable Internal Error Mask Register 6.6.2. Uncorrectable Internal Error Status Register 6.6.3. Correctable Internal Error Mask Register 6.6.4. Correctable Internal Error Status Register
7. Interrupts x
7.1. Interrupts for Endpoints 7.2. Interrupts for Root Ports
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. PCI Express Protocol Stack x
9.1. Top-Level Interfaces 9.2. Transaction Layer 9.3. Data Link Layer 9.4. Physical Layer
9.1. Top-Level Interfaces x
9.1.1. Avalon-ST Interface 9.1.2. Clocks and Reset 9.1.3. Local Management Interface (LMI Interface) 9.1.4. Hard IP Reconfiguration 9.1.5. Interrupts 9.1.6. PIPE
9.2. Transaction Layer x
9.2.1. Configuration Space
10. Transaction Layer Protocol (TLP) Details x
10.1. Supported Message Types 10.2. Transaction Layer Routing Rules 10.3. Receive Buffer Reordering
10.1. Supported Message Types x
10.1.1. INTX Messages 10.1.2. Power Management Messages 10.1.3. Error Signaling Messages 10.1.4. Locked Transaction Message 10.1.5. Slot Power Limit Message 10.1.6. Vendor-Defined Messages 10.1.7. Hot Plug Messages
10.3. Receive Buffer Reordering x
10.3.1. Using Relaxed Ordering
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Design Implementation x
12.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 12.2. Recommended Reset Sequence to Avoid Link Training Issues 12.3. SDC Timing Constraints
13. Additional Features x
13.1. Configuration over Protocol (CvP) 13.2. Autonomous Mode 13.3. ECRC
13.2. Autonomous Mode x
13.2.1. Enabling Autonomous Mode 13.2.2. Enabling CvP Initialization
13.3. ECRC x
13.3.1. ECRC on the RX Path 13.3.2. ECRC on the TX Path
15. Testbench and Design Example x
15.1. Endpoint Testbench 15.2. Test Driver Module 15.3. Root Port BFM Overview 15.4. BFM Procedures and Functions
15.1. Endpoint Testbench x
15.1.1. Endpoint Testbench for SR-IOV
15.3. Root Port BFM Overview x
15.3.1. BFM Memory Map 15.3.2. Configuration Space Bus and Device Numbering 15.3.3. Configuration of Root Port and Endpoint 15.3.4. Issuing Read and Write Transactions to the Application Layer
15.4. BFM Procedures and Functions x
15.4.1. ebfm_barwr Procedure 15.4.2. ebfm_barwr_imm Procedure 15.4.3. ebfm_barrd_wait Procedure 15.4.4. ebfm_barrd_nowt Procedure 15.4.5. ebfm_cfgwr_imm_wait Procedure 15.4.6. ebfm_cfgwr_imm_nowt Procedure 15.4.7. ebfm_cfgrd_wait Procedure 15.4.8. ebfm_cfgrd_nowt Procedure 15.4.9. BFM Configuration Procedures 15.4.10. BFM Shared Memory Access Procedures 15.4.11. BFM Log and Message Procedures 15.4.12. Verilog HDL Formatting Functions
15.4.9. BFM Configuration Procedures x
15.4.9.1. ebfm_cfg_rp_ep Procedure 15.4.9.2. ebfm_cfg_decode_bar Procedure
15.4.10. BFM Shared Memory Access Procedures x
15.4.10.1. Shared Memory Constants 15.4.10.2. shmem_write Task 15.4.10.3. shmem_read Function 15.4.10.4. shmem_display Verilog HDL Function 15.4.10.5. shmem_fill Procedure 15.4.10.6. shmem_chk_ok Function
15.4.11. BFM Log and Message Procedures x
15.4.11.1. ebfm_display Verilog HDL Function 15.4.11.2. ebfm_log_stop_sim Verilog HDL Function 15.4.11.3. ebfm_log_set_suppressed_msg_mask Task 15.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 15.4.11.5. ebfm_log_open Verilog HDL Function 15.4.11.6. ebfm_log_close Verilog HDL Function
15.4.12. Verilog HDL Formatting Functions x
15.4.12.1. himage1 15.4.12.2. himage2 15.4.12.3. himage4 15.4.12.4. himage8 15.4.12.5. himage16 15.4.12.6. dimage1 15.4.12.7. dimage2 15.4.12.8. dimage3 15.4.12.9. dimage4 15.4.12.10. dimage5 15.4.12.11. dimage6 15.4.12.12. dimage7
16. Debugging x
16.1. Simulation Fails To Progress Beyond Polling.Active State 16.2. Hardware Bring-Up Issues 16.3. Link Training 16.4. Creating a Signal Tap Debug File to Match Your Design Hierarchy 16.5. Use Third-Party PCIe Analyzer 16.6. BIOS Enumeration Issues
16.3. Link Training x
16.3.1. Link Hangs in L0 State
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
D. Document Revision History x
D.1. Document Revision History of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Quick Start Guide
3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History

D.1. Document Revision History of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

Date

Version

Changes Made

2021.06.03 18.0 Mentioned in the Features section that this IP supports the Separate Reference Clock No Spread Spectrum (SRNS) architecture and not the Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture.
2020.12.21 18.0 Fixed broken links.
2020.06.02 18.0

Changed the clock associated with the tl_cfg_add[3:0] and tl_cfg_sts[52:0] to coreclkout_hip in the Transaction Layer Configuration Space Signals section.

Updated the Configuration Space Register Access Timing section to state that the tl_cfg_add[3:0] and tl_cfg_ctl[31:0] update every eight coreclkout_hip cycles.

2020.03.19 18.0 Updated reset sequence and descriptions in Reset and Clocks to show that reset_status is the output that can be used to drive the reset of the Application Layer logic.
2019.12.20 18.0 Changed the name of the 1A state for the ltssmstate[4:0] signals to Recovery.Speed to follow the PCIe Specifications.
2019.12.02 18.0 Changed the description of the parameter BAR Size for Legacy Endpoint variants from 6 Bytes - 4 KB to 16 Bytes - 4 KB (for I/O space BARs).
2019.10.09 18.0 Added the 1F state (Recovery.Equalization, Done) for ltssmstate[4:0].
2019.05.22 18.0 Added a note clarifying that the 24-bit Class Code register consists of three 8-bit fields: Base Class Code, Sub-Class Code and Programming Interface.
2019.05.03 18.0 Updated the diagram for the reset sequence of the Hard IP for PCI Express IP Core and Application Layer to reflect the real behavior of reset_status.
2019.01.18 18.0

Removed the High and Maximum options for the RX buffer allocation parameter because they are not supported.

Changed the readyLatency of the RX interface to 3 cycles.

2018.12.28 18.0 Added a note clarifying that the IP core can support up to 256 tags only when in Configuration Bypass mode.
2018.09.11 18.0 Updated the description for pld_clk in the Clock Signals and Clock Summary sections. Also updated the clock domain in the timing diagrams in the Data Alignment and Timing for the 64-Bit Avalon-ST TX Interface section.
2018.08.13 18.0 Added the step to invoke Vsim to the instructions for running a ModelSim simulation.
2018.05.07 18.0

Replaced all references to Intel® Cyclone® 10 with Intel® Cyclone® 10 GX.

2017.10.14 17.1

Corrected typo: added optional parameter to invert the RX polarity, not the TX polarity.

2017.10.06 17.1 Made the following changes to the user guide:
  • Added support for Intel® Cyclone® 10 GX devices.
  • Removed the Getting Started with the Hard IP for PCI Express with the Avalon-ST Interface. The PCIe Quick Start Guide which downloads to hardware replaces it.
  • Corrected signal name, tx_cred_cons_sel should be tx_cons_cred_sel.

  • Revised the Testbench and Design Example chapter. Although the functions and tasks that implement the testbench have not changed, the organization of these functions and task in files is entirely different than in earlier device families.

  • Fixed minor errors and typos.
2017.05.26   Made the following changes to the user guide:
  • Added note that starting with the Intel® Quartus® Prime Pro Edition Software, version 17.0, the QSF assignments in the following answer What assignments do I need for a PCIe Gen1, Gen2 or Gen3 design that targets an Intel® Arria® 10 GX ES2, ES3 or production device? are already included in the design.
2017.05.12 17.0

Made the following changes the IP core:

  • Added option soft DFE Controller IP on the PHY tab of the parameter editor to improve BER margin. The default for this option is off because it is typically not required. Short reflective links may benefit from this soft DFE controller IP. This parameter is available only for Gen3 configurations. It is not supported when CvP or autonomous modes are enabled.

Made the following changes to the user guide:

  • Updated PCI Express Gen3 Bank Usage Restrictions status. These restrictions affect all Aria 10 ES and production devices.
  • Added statement that Intel® Arria® 10 devices do not support the Create timing and resource estimates for third-party EDA synthesis tools option on the Generate > Generate HDL menu.
  • Corrected default values for the Uncorrectable Internal Error Mask Register and Correctable Internal Error Mask Register registers.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Cores table. Out-of-order Completions are not supported transparently for the Avalon-MM with DMA interface.
  • Revised discussion of Application Layer Interrupt Handler Module to include legacy interrupt generation.
  • Corrected minor errors and typos.
2017.03.15 16.1.1

Made the following changes:

  • Restored Configuration Space Register Access topic which was inadvertently removed form previous versions.
  • Improved definitions of tx_cred_data_fc[11:0], tx_cred_fc_sel[1:0] and tx_cred_fdr_fc[7:0].
  • Added missing signal definition for tx_cred_fc_sel.
  • Added statement that Intel® Arria® 10 devices do not support the Create timing and resource estimates for third-party EDA synthesis tools option on the Generate > Generate HDL menu.
  • Rebranded as Intel.
2016.10.31 16.1

Made the following changes to the IP core:

  • Changed timing models support to final for most Intel® Arria® 10 device packages. Exceptions include some military and automotive speed grades with extended temperature ranges.
  • Added parameter to select the requested preset for Phase2 and Phase3 far-end TX equalization.

Made the following changes to the user guide:

  • Corrected the number of tags supported in the Feature Comparison for all Hard IP for PCI Express IP Cores table.
  • Removed recommendations about connecting pin_perst. These recommendations do not apply to Arria® 10 devices.
  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Corrected description of tl_cfg* bus. Provided sample RTL code to show how sample tl_cfg_ctl.Corrected tl_cfg_ctl Timing diagram.
  • Changed the recommended value of test_in[31:0] from 0xa8 to 0x188.
  • Added instructions for turning on autonomous mode in the Quartus Prime software.
  • Added -3 to recommended speed grades for the 125 MHz interface.
2016.05.02 16.0 Made the following changes:
  • The PIO Design Examples included in the Quick Start Guide now support 64- and 128-bit interfaces to the Application Layer. (The 15.1 release supported only a 256-bit interface to the Application Layer interface.)
  • The Quick Start Guide no longer supports the DMA design example.
  • Added support for Intel FPGA IP Evaluation Mode in the Quartus Prime Pro Edition software.
  • Added automatic generation of basic Signal Tap Logic Analyzer files to facilitate debugging.
  • Added figure for TX 3-dword header with qword aligned data.
  • Added Gen3 x2 128-bit interface with 125 MHz clock to the coreclkout_hip Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and Application Layer Interface Widths table.
  • In the Getting Started with the Hard IP for PCI Express chapter, changed the instructions to use specify the 10AX115S2F45I1SG device which is used on the Intel® Arria® 10 GX FPGA Development Kit - Production (not ES2) Edition.
  • Added statement that the testbench can only simulate a single Endpoint or Root Port at a time.
  • Enhanced statements covering the deficiencies of the Intel-provided testbench.
  • Added simulation support for Gen3 PIPE mode using the ModelSim, VCS, and NCSim simulators.
  • Added definition for rxfc_cplbuf_ovf.
  • Added Vendor Specific Extended Capability (VSEC) Revision and User Device or Board Type ID register from the Vendor Specific Extended Capability: to the VSEC tab of the component GUI.
  • Updated figures in Physical Layout of Hard IP in Intel® Arria® 10 Devices to include more detail about transceiver banks and channel restrictions.
  • Added transceiver bank usage placement restrictions for Gen3 devices.
  • Removed support for -3 speed grade devices.
  • Added transceiver bank usage placement restrictions for Gen3 devices.
  • Added -3 to recommended speed grades with qualifying statement.
  • Corrected minor errors and typos.
2015.11.30 15.1 Made the following changes:
  • Added definition for tx_fifo_empty signal.
  • Added figure illustrating data alignment for the TX 3-dword header with qword aligned address.
  • Added TLP Support Comparison for all Hard IP for PCI Express IP Cores in Datasheet chapter.
  • Added new topic on Autonomous Mode in which the Hard IP for PCI Express begins operation when the periphery configuration completes.
2015.11.02 15.1 Made the following changes:
  • Added auto generation of example designs for Endpoints that use the parameters you specify. Generation creates both simulation and hardware testbenches that you can download to the Intel® Arria® 10 FPGA Development Kit ES2 Edition. This new feature is described in the Intel® Arria® 10 Avalon-ST Quick Start Guide chapter of this user guide.
  • Added latency between tx_cred_fc_sel and tx_cred_data_fc and tx_cred_hdr_fc to the signal definitions.
  • Corrected instructions for changing between a serial and PIPE simulation.
  • Updated definitions of rxsynchd0[1:0] and rxblkst0 to say these signals can be grounded for Gen1 and Gen2 operation.
  • Improved the definition of npor.
  • Added note saying that the Hard IP for PCI Express supports autonomous mode when CvP is enabled.
  • In Transaction Layer Routing Rules, added Type 1 Message TLPs are also passed to the Application Layer.
  • Enhanced the definition of rx_st_mask.
  • Added x2 to the Lane Assignments without Lane Reversal table.
  • Removed signal definition for rx_st_be. This signal is not supported for Intel® Arria® 10 devices.
  • Changed the app_msi_req signal to X (don't care) in cycles 4 and 5 of the timing diagram, MSI Interrupt Signals Timing.
  • Removed Legacy Endpoint option for Port type parameters. The Legacy Endpoint is no longer supported for Intel® Arria® 10 devices.
  • Revised discussion on possible conflict between LMI writes and Host writes to the Configuration Space.
  • Removed Getting Started with the Configuration Space Bypass Model Platform Designer Example Design chapter. This example design is no longer supported.
  • Removed invalid warning about missing resets when this IP core is instantiated as a separate component from the Quartus® Prime IP Catalog.
  • Corrected Avalon-ST Hard IP for PCI Express Top-Level Signals figure and missing signal definitions.
2015.06.05 15.0 Added note in Physical Layout of Hard IP in Intel® Arria® 10 Devices to explain Intel® Arria® 10 design constraint that requires that if the lower HIP on one side of the device is configured with a Gen3 x4 or Gen3 x8 IP core, and the upper HIP on the same side of the device is also configured with a Gen3 IP core, then the upper HIP must be configured with a x4 or x8 IP core.
2015.05.04 15.0 Made the following changes to the Intel® Arria® 10 user guide:
  • Added to description of Data Link Layer link active bit. It is only available for Root Ports. It is always 0 for Endpoints.
  • Corrected link to Intel® Arria® 10 Avalon-MM DMA Interface for PCIe Solutions User Guide.
  • Added Enable Altera Debug Master Endpoint (ADME) parameter to support optional Native PHY register programming with the Altera System Console.
  • Added information about the custom example designs. This feature is available for this IP core starting in the IP core release 14.1.
  • Enhanced descriptions of channel placement, added fPLL placement for Gen1 and Gen2 data rates, and added master CGB location, in Physical Layout of Hard IP In Intel® Arria® 10 Devices.
  • Added column for Avalon-ST Interface with SR-IOV variations in Feature Comparison for all Hard IP for PCI Express IP Cores table in Features section. Moved supported TLPs information to separate table. Updated information in tables.
  • Removed Migration and TLP Format appendices, and added new appendix Frequently Asked Questions.
  • Corrected LMI Write figure in LMI Signals.
  • Corrected MSI-X Interrupt Components figure in Implementing MSI-X Interrupts.
  • Corrected width of rx_st_sop and rx_st_eop to 1 or two bits. If you turn on Enable multiple packets per cycle these signals have two bits; otherwise, they have one bit each. Refer to Avalon-ST RX Interface.
  • Removed non-existent signals rx_st_bar1 and rx_st_bar2. If you turn on Enable multiple packets per cycle, the IP core still has only a single rx_st_bar[7:0] signal. Do not use this signal if you turn on Enable multiple packets per cycle. Refer to iAvalon-ST RX Component Specific Signals.
  • Updated DUT module name in testbench and example design figures.
  • Reorganized sections in iDebugging and nik1410565029488.
  • Updated information in SDC Timing Constraints .
  • Fixed minor errors and typos.
2014.12.15 14.1 Made the following changes to the user guide:
  • Added simulation log file, altpcie_monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory. Generation of the log file requires the following simulation file, <install_dir>altera/altera_pcie/altera_pcie_<dev>_hip/altpcie_monitor_<dev>_dlhip_sim.sv, that was not present in earlier releases of the Quartus II software.
  • Changed device part number for Getting Started chapter to 10AX115R2F40I2LG.
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Removed 125 MHz clock as optional refclk frequency in Intel® Arria® 10 devices. Intel® Arria® 10 devices support an 100 MHz reference clock as specified by the PCI Express Base Specification, Rev 3.0.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Enhanced instructions Compiling the Design to include steps necessary to download to Altera development kits.
2014.08.18 14.0a10 Made the following changes to the Intel® Arria® 10 Hard IP for PCI Express:
  • Changed the PIPE interface to 32 bits for all data rates. This change requires you to recompile your 13.1 variant in 14.0.
  • Made fPLL available as the TX PLL for all data rates. This change allows you to use the ATX PLLs for higher data rate protocols if necessary.

Made the following changes to the user guide:

  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
2014.06.30 14.0

Added the following new features to the Intel® Arria® 10 Hard IP for PCI Express:

  • Added parameters to enable 256 completion tags with completion tag checking performed in Application Layer.
  • Added simulation log file, altpcie_monitor_sv_dlhip_tlp_file_log.log, that is automatically generated in your simulation directory. To simulation in the Quartus II 14.0 software release, you must regenerate your IP core to create the supporting monitor file the generates altpcie_monitor_sv_dlhip_tlp_file_log.log. Refer to Understanding Simulation Dump File Generation for details.
  • Added support for new parameter,User ID register from the Vendor Specific Extended Capability, for Endpoints.
  • Added parameter to create a reset pulse at power-up when the soft reset controller is enabled.
  • Simulation support for Phase 2 and Phase 3 equalization when requested by third-party BFM.
  • Increased size of lmi_addr to 15 bits.
  • Changed the directory structure for generated files. Refer to Files Generated for Intel FPGA IP Cores Targeting Arria 10 for more information.
  • In the Getting Started with the Intel® Arria® 10 Hard IP for PCI Express chapter, changed the recommended device to 10AX115R2F40I2LG (Advanced).

Made the following changes to the user guide:

  • Added Next Steps in Creating a Design for PCI Express to Datasheet chapter.
  • Corrected frequency range for hip_reconfig_clk. It should be 100-125 MHz.
  • Corrected Maximum payload size values listed in Reconfigurable Read-Only Registers table. The maximum size is 2048 bytes.
  • Enhanced definition of Device ID and Sub-system Vendor ID to say that these registers are only valid in the Type 0 (Endpoint) Configuration Space.
  • Changed the default reset controller settings. By default Gen1 devices use the Hard Reset Controller. Gen2 and Gen3 devices use the Soft Reset Controller.
  • Corrected frequencies of pclk in Reset and Clocks chapter.
  • Removed txdatavalid0 signal from the PIPE interface. This signal is not available.
  • Removed references to the MegaWizard® Plug-In Manager. In 14.0 the IP Parameter Editor Powered by Platform Designer has replaced the MegaWizard Plug-In Manager.
  • Made the following changes to the timing diagram, Hard IP Reconfiguration Bus Timing of Read-Only Registers:
    • Added hip_reconfig_rst_n.
    • Changed timing of avmm_rdata[15:0]. Valid data returns 4 cycles after avmm_rd.
  • Added link to a Knowledge Base Solution that shows how to observe the test_in bus for debugging.
  • Removed optional 125 MHz reference clock frequency. This option has not been tested extensively in hardware.
  • Corrected channel placement diagrams for Gen3 x2 and Gen3 x4. The CMU PLL should be shown in the Channel 4 location. For Gen3 x2, the second data channel is Ch1. For Gen3 x4, the data channels are Ch0 - Ch3.
  • Corrected figure showing physical placement of PCIe Hard IP modules for Arria V GZ devices.
  • Added definition for test_in[6] and link to Knowledge Base Solution on observing the PIPE interface signals on the test_out bus.
  • Removed references to Gen2 x1 62.5 MHz configuration. This configuration is not supported.
  • Removed statement that Gen1 and Gen2 designs do not require transceiver reconfiguration. Gen1 and Gen2 designs may require transceiver reconfiguration to improve signal quality.
  • Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver.
  • Removed soft reset controller .sdc constraints from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altpcied_<dev>.sdc example. These constraints are now in a separate file in the synthesis/submodules directory.
  • Updated Power Supply Voltage Requirements table.
  • For Intel® Arria® 10 devices, updated Physical Placement of the Intel® Arria® 10 Hard IP for PCIe IP and Channels to show GT devices instead of GX devices.
  • For Intel® Arria® 10 devices, corrected frequency of hip_reconfig_lck. I should be 125 MHz.
2013.12.20 13.1 Made the following changes:
  • Divided user guide into 3 separate documents by interface type.
  • Added Design Implementation chapter.
  • In the Debugging chapter, removed section explaining how to turn off the scrambler for Gen3 because it does not work.
  • In the Debugging chapter, corrected filename that you must change to reduce counter values in simulation.
  • In Getting Started with the Avalon-MM Hard IP for PCI Express chapter, corrected connects for the Transceiver Reconfiguration Controller IP Core reset signal, alt_xcvr_reconfig_0 mgmt_rst_reset. This reset input connects to clk_0 clk_reset.
  • In Transaction Layer Routing Rules and Programming Model for Avalon-MM Root Port added the fact that Type 0 Configuration Requests sent to the Root Port are not filtered by the device number. Application Layer software must filter out requests for device number greater than 0.
  • Added illustration showing the location of the Hard IP Cores in the Intel® Arria® 10 devices.
  • Added limitation for rxm_irq_<n>[<m>:0]when interrupts are received on consecutive cycles.
  • Corrected description of cfg_prm_cmr. It is the Base/Primary Command register for the PCI Configuration Space.
  • Revised channel placement illustrations.

2013.05.06

13.0

  • Added support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions
  • Added preliminary support for a Avalon-MM 256-Bit Hard IP for PCI Express that is capable of running at the Gen3 ×8 data rate. This new IP Core. Refer to the Avalon-MM 256-Bit Hard IP for PCI Express User Guide for more information.
  • Added Gen3 PIPE simulation support.
  • Added support for 64-bit address in the Avalon-MM Hard IP for PCI Express IP Core, making address translation unnecessary
  • Added instructions for running the Single Dword variant.
  • Timing models are now final.
  • Updated the definition of refclk to include constraints when CvP is enabled.
  • Added section covering clock connectivity for reconfiguration when CvP is enabled.
  • Corrected access field in Root Port TLP Data registers.
  • Added Getting Started chapter for Configuration Space Bypass mode.
  • Added signal and register descriptions for the Gen3 PIPE simulation.
  • Added 64-bit addressing for the Avalon-MM IP Cores for PCI Express.
  • Changed descriptions of rx_st_err[1:0], tx_st_err[1:0], rx_st_valid[1:0], and tx_st_valid[1:0] buses. Bit 1 is not used.
  • Corrected definitions of RP_RXCPL_STATUS.SOP and RP_RXCPL_STATUS.EOP bits. SOP is 0x2010, bit[0] and EOP is 0x2010, bit[1].
  • Improved explanation of relaxed ordering of transactions and provided examples.
  • Revised discussion of Transceiver Reconfiguration Controller IP Core. Offset cancellation is not required for Gen1 or Gen2 operation.

2011.07.30

11.01

Corrected typographical errors.

2011.05.06

11.0

First release.

Level Two Title