Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

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ID 683647
Date 6/03/2021
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Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Quick Start Guide 3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings 4. Physical Layout 5. Interfaces and Signal Descriptions 6. Registers 7. Interrupts 8. Error Handling 9. PCI Express Protocol Stack 10. Transaction Layer Protocol (TLP) Details 11. Throughput Optimization 12. Design Implementation 13. Additional Features 14. Hard IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Transaction Layer Packet (TLP) Header Formats B. Lane Initialization and Reversal C. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive D. Document Revision History
1. Datasheet x
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Debug Features 1.6. IP Core Verification 1.7. Resource Utilization 1.8. Recommended Speed Grades 1.9. Creating a Design for PCI Express
1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet x
1.1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Features
1.6. IP Core Verification x
1.6.1. Compatibility Testing Environment
2. Quick Start Guide x
2.1. Directory Structure 2.2. Design Components 2.3. Generating the Design 2.4. Simulating the Design 2.5. Compiling and Testing the Design in Hardware
3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings x
3.1. Parameters 3.2. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Settings 3.3. Base Address Register (BAR) and Expansion ROM Settings 3.4. Base and Limit Registers for Root Ports 3.5. Device Identification Registers 3.6. PCI Express and PCI Capabilities Parameters 3.7. Vendor Specific Extended Capability (VSEC) 3.8. Configuration, Debug, and Extension Options 3.9. PHY Characteristics 3.10. Example Designs
3.6. PCI Express and PCI Capabilities Parameters x
3.6.1. PCI Express and PCI Capabilities 3.6.2. Error Reporting 3.6.3. Link Capabilities 3.6.4. MSI and MSI-X Capabilities 3.6.5. Slot Capabilities 3.6.6. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Intel® Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Intel® Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions x
5.1. Clock Signals 5.2. Reset, Status, and Link Training Signals 5.3. ECRC Forwarding 5.4. Error Signals 5.5. Interrupts for Endpoints 5.6. Interrupts for Root Ports 5.7. Completion Side Band Signals 5.8. Parity Signals 5.9. LMI Signals 5.10. Transaction Layer Configuration Space Signals 5.11. Hard IP Reconfiguration Interface 5.12. Power Management Signals 5.13. Physical Layer Interface Signals
5.10. Transaction Layer Configuration Space Signals x
5.10.1. Configuration Space Register Access Timing 5.10.2. Configuration Space Register Access
5.13. Physical Layer Interface Signals x
5.13.1. Serial Data Signals 5.13.2. PIPE Interface Signals 5.13.3. Test Signals 5.13.4. Intel® Arria® 10 Development Kit Conduit Interface
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. Advanced Error Reporting Capability
6.5. Intel-Defined VSEC Registers x
6.5.1. CvP Registers
6.6. Advanced Error Reporting Capability x
6.6.1. Uncorrectable Internal Error Mask Register 6.6.2. Uncorrectable Internal Error Status Register 6.6.3. Correctable Internal Error Mask Register 6.6.4. Correctable Internal Error Status Register
7. Interrupts x
7.1. Interrupts for Endpoints 7.2. Interrupts for Root Ports
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. PCI Express Protocol Stack x
9.1. Top-Level Interfaces 9.2. Transaction Layer 9.3. Data Link Layer 9.4. Physical Layer
9.1. Top-Level Interfaces x
9.1.1. Avalon-ST Interface 9.1.2. Clocks and Reset 9.1.3. Local Management Interface (LMI Interface) 9.1.4. Hard IP Reconfiguration 9.1.5. Interrupts 9.1.6. PIPE
9.2. Transaction Layer x
9.2.1. Configuration Space
10. Transaction Layer Protocol (TLP) Details x
10.1. Supported Message Types 10.2. Transaction Layer Routing Rules 10.3. Receive Buffer Reordering
10.1. Supported Message Types x
10.1.1. INTX Messages 10.1.2. Power Management Messages 10.1.3. Error Signaling Messages 10.1.4. Locked Transaction Message 10.1.5. Slot Power Limit Message 10.1.6. Vendor-Defined Messages 10.1.7. Hot Plug Messages
10.3. Receive Buffer Reordering x
10.3.1. Using Relaxed Ordering
11. Throughput Optimization x
11.1. Throughput of Posted Writes 11.2. Throughput of Non-Posted Reads
12. Design Implementation x
12.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 12.2. Recommended Reset Sequence to Avoid Link Training Issues 12.3. SDC Timing Constraints
13. Additional Features x
13.1. Configuration over Protocol (CvP) 13.2. Autonomous Mode 13.3. ECRC
13.2. Autonomous Mode x
13.2.1. Enabling Autonomous Mode 13.2.2. Enabling CvP Initialization
13.3. ECRC x
13.3.1. ECRC on the RX Path 13.3.2. ECRC on the TX Path
15. Testbench and Design Example x
15.1. Endpoint Testbench 15.2. Test Driver Module 15.3. Root Port BFM Overview 15.4. BFM Procedures and Functions
15.1. Endpoint Testbench x
15.1.1. Endpoint Testbench for SR-IOV
15.3. Root Port BFM Overview x
15.3.1. BFM Memory Map 15.3.2. Configuration Space Bus and Device Numbering 15.3.3. Configuration of Root Port and Endpoint 15.3.4. Issuing Read and Write Transactions to the Application Layer
15.4. BFM Procedures and Functions x
15.4.1. ebfm_barwr Procedure 15.4.2. ebfm_barwr_imm Procedure 15.4.3. ebfm_barrd_wait Procedure 15.4.4. ebfm_barrd_nowt Procedure 15.4.5. ebfm_cfgwr_imm_wait Procedure 15.4.6. ebfm_cfgwr_imm_nowt Procedure 15.4.7. ebfm_cfgrd_wait Procedure 15.4.8. ebfm_cfgrd_nowt Procedure 15.4.9. BFM Configuration Procedures 15.4.10. BFM Shared Memory Access Procedures 15.4.11. BFM Log and Message Procedures 15.4.12. Verilog HDL Formatting Functions
15.4.9. BFM Configuration Procedures x
15.4.9.1. ebfm_cfg_rp_ep Procedure 15.4.9.2. ebfm_cfg_decode_bar Procedure
15.4.10. BFM Shared Memory Access Procedures x
15.4.10.1. Shared Memory Constants 15.4.10.2. shmem_write Task 15.4.10.3. shmem_read Function 15.4.10.4. shmem_display Verilog HDL Function 15.4.10.5. shmem_fill Procedure 15.4.10.6. shmem_chk_ok Function
15.4.11. BFM Log and Message Procedures x
15.4.11.1. ebfm_display Verilog HDL Function 15.4.11.2. ebfm_log_stop_sim Verilog HDL Function 15.4.11.3. ebfm_log_set_suppressed_msg_mask Task 15.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 15.4.11.5. ebfm_log_open Verilog HDL Function 15.4.11.6. ebfm_log_close Verilog HDL Function
15.4.12. Verilog HDL Formatting Functions x
15.4.12.1. himage1 15.4.12.2. himage2 15.4.12.3. himage4 15.4.12.4. himage8 15.4.12.5. himage16 15.4.12.6. dimage1 15.4.12.7. dimage2 15.4.12.8. dimage3 15.4.12.9. dimage4 15.4.12.10. dimage5 15.4.12.11. dimage6 15.4.12.12. dimage7
16. Debugging x
16.1. Simulation Fails To Progress Beyond Polling.Active State 16.2. Hardware Bring-Up Issues 16.3. Link Training 16.4. Creating a Signal Tap Debug File to Match Your Design Hierarchy 16.5. Use Third-Party PCIe Analyzer 16.6. BIOS Enumeration Issues
16.3. Link Training x
16.3.1. Link Hangs in L0 State
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
D. Document Revision History x
D.1. Document Revision History of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Quick Start Guide
3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Interrupts
8. Error Handling
9. PCI Express Protocol Stack
10. Transaction Layer Protocol (TLP) Details
11. Throughput Optimization
12. Design Implementation
13. Additional Features
14. Hard IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History

1.1. Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet

Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively. The Hard IP for PCI Express* using the Avalon® Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough understanding of the PCI Express* Protocol.

Figure 1.  Intel® Arria® 10 or Intel® Cyclone® 10 GX Variant with Avalon-ST Interface

The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, and 8 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga‑transfers per second for Gen3. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to about 1.5%.

Table 1.  PCI Express Data Throughput
Link Width
×1 ×2 ×4 ×8

PCI Express Gen1 (2.5 Gbps)

2

4

8

16

PCI Express Gen2 (5.0 Gbps)

4

8

16

32

PCI Express Gen3 (8.0 Gbps)

7.87

15.75

31.51

63

The following table shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 for 1, 2, and 4 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5.0 giga-transfers per second for Gen2. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.

Table 2.  PCI Express Data Throughput
Link Width
  ×1 ×2 ×4

PCI Express Gen1 (2.5 Gbps)

2

4

8

PCI Express Gen2 (5.0 Gbps)

4

8

16

Refer to the AN 456: PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Intel FPGAs, including the Intel® Arria® 10 Hard IP for PCI Express IP core.

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Intel Arria 10 or Intel Cyclone 10 GX Features

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