Intel® Stratix® 10 H-tile and L-tile Avalon® Memory-mapped Hard IP for PCI Express* Design Example User Guide

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ID 683616
Date 3/07/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Design Components 1.2. Hardware and Software Requirements 1.3. Directory Structure 1.4. Generating the Design Example 1.5. Simulating the Design Example 1.6. Compiling the Design Example and Programming the Device 1.7. Installing the Linux Kernel Driver 1.8. Running the Design Example Application
2. Design Example Description x
2.1. Functional Description for the DMA Design Example 2.2. Serial Data Signals
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide x
A.1. Intel® Stratix® 10 H-tile and L-tile Avalon® memory mapped Hard IP for PCI Express* Design Example User Guide Revision History
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

1.5. Simulating the Design Example

Figure 6. Procedure
  1. Change to the testbench simulation directory, pcie_example_design_tb.
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
Table 1.  Steps to Run Simulation
Simulator Working Directory Instructions
ModelSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/mentor/
  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
    Note: Alternatively, instead of doing Steps 1 and 2, you can type: vsim -c -do msim_setup.tcl.
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
VCS* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/synopsys/vcs
  1. sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
NCSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/cadence
  1. sh ncsim_setup.sh USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps"
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
Xcelium* Parallel Simulator <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/xcelium
  1. sh xcelium_setup.sh USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS ="-timescale\ 1ns/1ps\ -NOWARN\ CSINFI"
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
The DMA testbench completes the following tasks:
  1. Writes to the Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
  2. Reads from Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
  3. Verifies the data using the shmem_chk_ok task.
  4. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MRd request to the PCIe* address space in host memory.
  5. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MWr request to PCIe* address space in host memory. This MWr uses the data from the previous MRd.
  6. Verifies the data using the shmem_chk_ok task.

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

Figure 7. Partial Transcript from Successful Simulation Testbench
Level Two Title