Intel® Stratix® 10 H-tile and L-tile Avalon® Memory-mapped Hard IP for PCI Express* Design Example User Guide

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ID 683616
Date 3/07/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Design Components 1.2. Hardware and Software Requirements 1.3. Directory Structure 1.4. Generating the Design Example 1.5. Simulating the Design Example 1.6. Compiling the Design Example and Programming the Device 1.7. Installing the Linux Kernel Driver 1.8. Running the Design Example Application
2. Design Example Description x
2.1. Functional Description for the DMA Design Example 2.2. Serial Data Signals
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide x
A.1. Intel® Stratix® 10 H-tile and L-tile Avalon® memory mapped Hard IP for PCI Express* Design Example User Guide Revision History
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for the Intel® Stratix® 10 Avalon® -MM Hard IP for PCIe* Design Example User Guide

1.6. Compiling the Design Example and Programming the Device

  1. Navigate to <project_dir>/pcie_s10_hip_avmm_bridge_0_example_design/ and open pcie_example_design.qpf.
  2. On the Processing menu, select Start Compilation.
  3. After successfully compiling your design, program the targeted device with the Programmer.
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