Intel® Stratix® 10 SEU Mitigation User Guide

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ID 683602
Date 12/30/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
1. Intel® Stratix® 10 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices 1.2. Configuration RAM 1.3. Memory Blocks Error Correction Code (ECC) Support 1.4. Secure Device Manager ECC Error 1.5. Triple-Module Redundancy 1.6. Failure Rates
2. Intel® Stratix® 10 Mitigation Techniques for CRAM x
2.1. CRAM Error Detection and Correction 2.2. Internal Scrubbing and Priority Scrubbing 2.3. SEU Sensitivity Processing 2.4. Designating the Sensitivity of the Design Hierarchy 2.5. Evaluating a System's Response to Functional Upsets
2.1. CRAM Error Detection and Correction x
2.1.1. Error Message Queue 2.1.2. SEU_ERROR Pin Behavior
2.2. Internal Scrubbing and Priority Scrubbing x
2.2.1. Internal Scrubbing 2.2.2. Priority Scrubbing
2.3. SEU Sensitivity Processing x
2.3.1. Advanced SEU Detection IP Core
2.3.1. Advanced SEU Detection IP Core x
2.3.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.3.1.2. On-Chip Lookup Sensitivity Processing 2.3.1.3. Off-Chip Lookup Sensitivity Processing 2.3.1.4. SMH Lookup
2.3.1.3. Off-Chip Lookup Sensitivity Processing x
2.3.1.3.1. Off-Chip Lookup Sensitivity Processing Operation Flow
2.3.1.4. SMH Lookup x
2.3.1.4.1. SMH Revision 4 File Format
2.4. Designating the Sensitivity of the Design Hierarchy x
2.4.1. Hierarchy Tagging
2.5. Evaluating a System's Response to Functional Upsets x
2.5.1. Intel® Quartus® Prime Fault Injection Debugger
3. Secure Device Manager ECC Error Detection x
3.1. SDM ECC Error Message Bits 3.2. SDM ECC Error Signals Behavior
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides x
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
4.7. Using the Fault Injection Debugger x
4.7.1. Enabling the Fault Injection Debugger 4.7.2. Launching and Setting Up the Fault Injection Debugger 4.7.3. Configuring Your Device and the Fault Injection Debugger 4.7.4. Constraining Regions for Fault Injection 4.7.5. Injecting Errors 4.7.6. Injecting Double Adjacent Errors
4.7.5. Injecting Errors x
4.7.5.1. Injecting Errors to a Random Location 4.7.5.2. Injecting Errors to a Specific Location
4.7.6. Injecting Double Adjacent Errors x
4.7.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.7.6.2. Injecting Double Adjacent Errors: GUI
4.9. Intel® Quartus® Prime Software SEU FIT Reports x
4.9.1. Enabling the Projected SEU FIT by Component Usage Report 4.9.2. SEU FIT Parameters Report 4.9.3. Projected SEU FIT by Component Usage Report
4.9.3. Projected SEU FIT by Component Usage Report x
4.9.3.1. Component FIT Rates 4.9.3.2. Raw FIT 4.9.3.3. Utilized FIT 4.9.3.4. Mitigated FIT 4.9.3.5. Architectural Vulnerability Factor
4.9.3.3. Utilized FIT x
4.9.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 4.9.3.3.2. Considerations for Small Designs
5. Advanced SEU Detection Intel® FPGA IP References x
5.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.2. Advanced SEU Detection IP Core Ports
6. Intel® Stratix® 10 Fault Injection Debugger References x
6.1. Fault Injection Debugger Interface Parameters 6.2. Fault Injection Debugger Command-Line Interface
1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide

8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.12.30 21.3
  • Updated subsection: CRAM Error Detection and Correction.
  • Updated subsection: Scrubbing.
2022.09.26 21.3
  • Added note in Advanced SEU Detection IP Core.
  • Added note in Minimum SEU interval setting in Intel Quartus Prime SEU Software Settings.
  • Removed the footnote in Table: Advanced SEU Detection Intel® FPGA IP Core Current Release Information.
2021.10.28 21.3
  • Increased the error message queue storage from a maximum of four messages to eight messages.
  • Added information about the actual minimum SEU interval being higher than the value you specify.
  • Added support for SDM ECC error detection.
  • Added section about the Intel® Quartus® Prime software SEU FIT reports.
  • Added steps to analyze SEU errors using Signal Tap.
2021.07.05 21.2
  • Added support for injecting double adjacent errors.
  • Updated the Advanced SEU Detection IP core ports.
2021.04.15 21.1
  • Updated the error message queue table to update the description for bit 31:29.
  • Updated the topic about internal scrubbing to improve clarity and add information about uncorrectable errors.
  • Updated the topic about priority scrubbing to improve clarity.
  • Updated the quartus_fid command and arguments, and added examples.
  • Updated the Intel® Quartus® Prime SEU software settings to add the option to turn on Allow SEU fault injection.
  • Updated the off-chip sensitivity processing ports information of the Advanced SEU Detection IP.
  • Updated the following signal names:
    • seu_avst_data to avst_seu_source_data
    • seu_avst_valid to avst_seu_source_valid
    • seu_avst_ready to avst_seu_source_ready
  • Updated "Avalon-MM" and "Avalon-ST" to " Avalon® memory-mapped interface" and " Avalon® streaming interface".
2020.09.24 20.2 Updated the procedures for using the Fault Injection Debugger to improve clarity.
2019.10.16 19.3
  • Updated the procedures in the Programming Sensitivity Map Header File into Memory topic from using the Convert Programming File tool to using the Programming File Generator tool.
  • Updated the topic about failure rates to correct the number of years of one billion hours.
  • Removed the footnote about future Intel® Quartus® Prime support for double adjacent errors and multiple bit errors. The features are now supported in the Intel® Quartus® Prime software.
  • Updated the footnote to the "Error location" entry in the Error Message Queue Description table to clarify the different return values for single bit error with or without internal scrubbing.
  • Updated the Advanced SEU Detection Intel® FPGA IP to version 19.1.0:
    • Changed the IP name from "Advanced SEU Detection Intel® Stratix® 10 FPGA IP" to "Advanced SEU Detection Intel® FPGA IP".
    • Updated the description for the SEU error fifo depth parameter to remove the condition that it is available only if you turn on Use on-chip processing. SEU error fifo depth parameter is available for on-chip and off-chip sensitivity processing.
2019.07.01 19.2 Updated the table listing the error message queue description to clarify that the bit position of the sector address and error location fields on the seu_avst_data signal.
2019.05.17 19.1 Added a note to the reset port regarding IP core instantiation guidelines in the tables about Advanced SEU Detection IP core on-chip and off-chip sensitivity processing ports.
2018.10.10 18.1
  • Removed correction support for double adjacent errors.
  • Updated the topic about the error message queue to remove mention of error count in the error message queue.
  • Added a topic about internal scrubbing.
  • Added a topic about priority scrubbing.
  • Updated the topic about setting the Intel® Quartus® Prime SEU settings to improve clarity.
  • Added procedures for enabling priority scrubbing.
  • Updated the allowed value of the Largest ASD region ID used parameter from "1 to 255" to "1 to 32".
2018.08.07 18.0
  • Removed correction support for multiple bit errors.
  • Corrected the signal names in the topic about off-chip lookup sensitivity processing from seu_avst_ready to seu_avst_valid.
  • Updated IP core name from "Intel® FPGA Stratix® 10 Advanced SEU Detection IP" to "Advanced SEU Detection Intel® FPGA Stratix® 10 IP".
2018.05.07 18.0
  • Added smh argument to the Fault Injection command-line interface command.
  • Updated the user command in Fault Injection command-line interface description.
  • Added Failure Rates section.
  • Added Constraining Regions for Fault Injection section.
  • Updated argument to inject error on specific location.
  • Updated the ECC status flag signals for eSRAM blocks in the Memory Blocks Error Correction Code Support topic.
Date Version Changes
December 2017 2017.12.29
  • Added Fault Injection tool information.
  • Added the Advanced SEU Detection IP core information.
  • Updated Implementation Guide to include Fault Injection tool and Advanced SEU Detection IP core implementations.
  • Restructured Overview chapter.
December 2016 2016.12.09
  • Added SEU_ERROR Pin Settings.
  • Added Enabling Internal Scrubbing.
October 2016 2016.10.31 Initial release.
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