R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 6/20/2022
Public

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2.3.1.2. VCS* Simulator

Perform the following steps to execute the simulation via a command line:
  1. Change to the simulation working directory: cd <my_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs.
  2. Execute the following command: sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log
    Note: The command above is a single-line command.

A successful simulation includes the following message: "Simulation stopped due to successful completion!"

Perform the following steps to execute the simulation in interactive mode. Note that in case you have already generated a simv executable in non-interactive mode, you need to delete the simv file and simv.diadir directory.
  1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -kdb -debug_access+all
  2. Execute the following command: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" SKIP_SIM=1 TOP_LEVEL_NAME="pcie_ed_tb"
  3. Start the simulation in interactive mode: simv -gui &