R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683544
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. About the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express PIO Design Example 2. Quick Start Guide 3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express Design Example User Guide
1. About the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express PIO Design Example x
1.1. Credit Initialization Sequence 1.2. Hardware and Software Requirements
1.1. Credit Initialization Sequence x
1.1.1. Credit Value Initialization and Return 1.1.2. Credit Distribution
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Root Port BFM 2.5. Compiling the Design Example 2.6. Installing the Linux Kernel Driver 2.7. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Siemens EDA QuestaSim* Simulator 2.3.1.2. VCS* Simulator 2.3.1.3. VCS* MX Simulator 2.3.1.4. Xcelium* Simulator
2.3.2. Testbench x
2.3.2.1. Testbench Modules 2.3.2.2. Test Driver Module 2.3.2.3. PIO Design Example
2.4. Root Port BFM x
2.4.1. BFM Memory Map 2.4.2. Configuration Space Bus and Device Numbering 2.4.3. Configuration of Root Port and Endpoint 2.4.4. Issuing Read and Write Transactions to the Application Layer 2.4.5. BFM Procedures and Functions
2.4.5. BFM Procedures and Functions x
2.4.5.1. ebfm_barwr Procedure 2.4.5.2. ebfm_barwr_imm Procedure 2.4.5.3. ebfm_barrd_wait Procedure 2.4.5.4. ebfm_barrd_nowt Procedure 2.4.5.5. ebfm_cfgwr_imm_wait Procedure 2.4.5.6. ebfm_cfgwr_imm_nowt Procedure 2.4.5.7. ebfm_cfgrd_wait Procedure 2.4.5.8. ebfm_cfgrd_nowt Procedure 2.4.5.9. BFM Configuration Procedures 2.4.5.10. BFM Shared Memory Access Procedures 2.4.5.11. BFM Log and Message Procedures 2.4.5.12. Verilog HDL Formatting Functions
2.4.5.9. BFM Configuration Procedures x
2.4.5.9.1. ebfm_cfg_rp_ep Procedure 2.4.5.9.2. ebfm_cfg_decode_bar Procedure
2.4.5.10. BFM Shared Memory Access Procedures x
2.4.5.10.1. Shared Memory Constants 2.4.5.10.2. shmem_write Task 2.4.5.10.3. shmem_read Function 2.4.5.10.4. shmem_display Verilog HDL Function 2.4.5.10.5. shmem_fill Procedure 2.4.5.10.6. shmem_chk_ok Function
2.4.5.11. BFM Log and Message Procedures x
2.4.5.11.1. ebfm_display Verilog HDL Function 2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function 2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task 2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 2.4.5.11.5. ebfm_log_open Verilog HDL Function 2.4.5.11.6. ebfm_log_close Verilog HDL Function
2.4.5.12. Verilog HDL Formatting Functions x
2.4.5.12.1. himage1 2.4.5.12.2. himage2 2.4.5.12.3. himage4 2.4.5.12.4. himage8 2.4.5.12.5. himage16 2.4.5.12.6. dimage1 2.4.5.12.7. dimage2 2.4.5.12.8. dimage3 2.4.5.12.9. dimage4 2.4.5.12.10. dimage5 2.4.5.12.11. dimage6 2.4.5.12.12. dimage7
2.7. Running the Design Example x
2.7.1. Running the PIO Design Example
1. About the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express PIO Design Example
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express Design Example User Guide

1. About the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express PIO Design Example

Updated for:
Intel® Quartus® Prime Design Suite 22.2
IP Version 6.0.0

The Programmed Input/Output (PIO) design example performs memory transfers from a host processor to a target device. In this example, the host processor requests single-dword Memory Read (MemRd) and Memory Write (MemWr) Transaction Layer Packets (TLPs).

The PIO design example automatically creates the files necessary to simulate and compile in the Intel® Quartus® Prime software. The design example covers a wide range of parameters. However, it does not cover all possible parameterizations of the R-tile Hard IP for PCIe.

This design example supports the following configurations:

Table 1.  Design Example Configurations Support
Port Mode Link Width Lin Speed Data Width (Bits) Design Example Support Simulators Supported
Endpoint x16 Gen5 1024 (4 x 256) SCTH Siemens EDA QuestaSim* , VCS* , VCS* MX, Xcelium* 2
Gen4 1024 (4 x 256) SCTH 1 Siemens EDA QuestaSim* , VCS* , VCS* MX, Xcelium* 2
512 (2 x 256) N/A N/A
Gen3 1024 (4 x 256) SCTH 1 Siemens EDA QuestaSim* , VCS* , VCS* MX, Xcelium* 2
512 (2 x 256) N/A N/A
x8 Gen5 512 (2 x 256) SCTH 1 Siemens EDA QuestaSim* , VCS* , VCS* MX, Xcelium* 2
Gen4 512 (2 x 256) SCTH 1 Siemens EDA QuestaSim* , VCS* , VCS* MX, Xcelium* 2
256 (1 x 256) N/A N/A
Gen3 512 (2 x 256) SCTH 1 Siemens EDA QuestaSim* , VCS* , VCS* MX, Xcelium* 2
256 (1 x 256) N/A N/A
x4 Gen5 256 (2 x 128) N/A N/A
Gen4 256 (2 x 128) N/A N/A
128 (1 x 128) N/A N/A
Gen3 256 (2 x 128) N/A N/A
128 (1 x 128) N/A N/A
Root Port N/A N/A N/A N/A N/A
TLP Bypass N/A N/A N/A N/A N/A
PIPE-D N/A N/A N/A N/A N/A

The clock comes from the coreclkout_hip output of the IP and runs at 500 MHz.

Note: In the 22.2 release of Intel® Quartus® Prime, this design example only supports the default settings in the Parameter Editor of the R-tile Avalon® Streaming IP for PCIe.
This design example includes the following components:
  • The generated R-tile Avalon® Streaming (Avalon-ST) Hard IP Endpoint variant (DUT) with the parameters you specified. This component drives TLP data received to the PIO application. It translates the PCIe serial data received from the link to the Avalon® -ST data format.
  • The PIO Application (APPS) component, which performs the necessary translation between the PCI Express TLPs and simple Avalon® Memory-mapped ( Avalon® -MM) writes and reads to the on-chip memory.
    Note: The current APPS component supports only single-cycle data transfers. Data transfers longer than one clock cycle are not supported.
  • An on-chip memory (MEM) component (one 32 KB memory for the x16 design example, and two 32 KB memories for the 2x8 design example).
  • Reset Release IP: This IP holds the control circuit in reset until the device has fully entered user mode. The FPGA asserts the nINIT_DONE output to signal that the device is in user mode. The nINIT_DONE signal is high until the entire device enters user mode. After nINIT_DONE deasserts (low), all logic is in user mode and operates normally.

The Gen5 x16 design example instantiates a PIO component with a 1024-bit data path to interface with the 1024-bit DUT. Also, the design example instantiates only one MEM device as shown in the figure below.

Figure 1. Gen5 x16 Design Example Block Diagram

The Gen5 2x8 design example instantiates two PIO components with 512-bit data paths to interface with the 2x512-bit DUT. Also, the design example instantiates two MEM devices as shown in the figure below.

Figure 2. Gen5 2x8 Design Example Block Diagram

For simulation purposes, this design example also generates a testbench that instantiates the PIO design example and a Root Port BFM to interface with the target Endpoint.

Note: The simulation testbench for the PCIe 2x8 PIO design example has a single PCIe x8 link although the actual design implements two PCIe x8 links.
Figure 3. Block Diagram for the Platform Designer PIO Design Example Simulation Testbench

The test program writes to and reads back data from the same location in the on-chip memory. It compares the data read to the expected result. The test reports, "Simulation stopped due to successful completion" if no errors occur.

Figure 4.  Platform Designer System Contents for the R-tile Avalon® -ST PCI Express Gen5 x16 PIO Design Example
Figure 5.  Platform Designer System Contents for the R-tile Avalon® -ST PCI Express Gen5 2x8 PIO Design Example

Section Content
Credit Initialization Sequence
Hardware and Software Requirements

1 The R-tile Avalon® Streaming Intel FPGA IP for PCI Express design example has limited hardware testing support in the 22.2 release of Intel® Quartus® Prime. Use instructions starting in section 2.5 for early testing and for the flow required to run the design example on the Intel® Agilex™ I-Series FPGA Development Kit.
2 Xcelium* simulator support is only available in devices with the suffix R2 or R3 in their OPN numbers. For more details on OPN decoding, refer to the Intel® Agilex™ FPGAs and SoCs Device Overview.
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