Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

6.9.2. XGMII RX Signals

The signals below are present in the following operating modes: 10G, 1G/10G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, and 10M/100M/1G/2.5G/10G.

Table 48.  XGMII Receive Signals
Signal Condition Direction Width Description
xgmii_rx_data[]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode disabled.

In 32 4-lane RX data bus. Lane 0 starts from the least significant bit.
  • Lane 0: xgmii_rx_data[7:0]
  • Lane 1: xgmii_rx_data[15:8]
  • Lane 2: xgmii_rx_data[23:16]
  • Lane 3: xgmii_rx_data[31:24]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode enabled.

In 64

8-lane SDR XGMII receive data. This signal connects directly to the Native PHY IP core.

  • Lane 0: xgmii_rx_data[7:0]
  • Lane 1: xgmii_rx_data[15:8]
  • Lane 2: xgmii_rx_data[23:16]
  • Lane 3: xgmii_rx_data[31:24]
  • Lane 4: xgmii_rx_data[39:32]
  • Lane 5: xgmii_rx_data[47:40]
  • Lane 6: xgmii_rx_data[55:48]
  • Lane 7: xgmii_rx_data[63:56]
xgmii_rx_control[]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode disabled.

In 4 Control bits for each lane in xgmii_rx_data[].
  • Lane 0: xgmii_rx_control[0]
  • Lane 1: xgmii_rx_control[1]
  • Lane 2: xgmii_rx_control[2]
  • Lane 3: xgmii_rx_control[3]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode enabled.

In 8

8-lane SDR XGMII receive control. This signal connects directly to the NativePHY IP core.

  • Lane 0: xgmii_rx_control[0]
  • Lane 1: xgmii_rx_control[1]
  • Lane 2: xgmii_rx_control[2]
  • Lane 3: xgmii_rx_control[3]
  • Lane 4: xgmii_rx_control[4]
  • Lane 5: xgmii_rx_control[5]
  • Lane 6: xgmii_rx_control[6]
  • Lane 7: xgmii_rx_control[7]
xgmii_rx_valid

Use legacy Ethernet 10G MAC XGMII interface disabled.

(Enable 10GBASE-R register mode or Speed is set to 100M/100M/1G/2.5G/5G/10G (USXGMII))

In 1 When asserted, indicates that the data and control buses are valid.
xgmii_rx[] Use legacy Ethernet 10G MAC XGMII interface enabled. In 72

8-lane SDR XGMII receive data and control bus. Each lane contains 8 data plus 1 control bits. The signal mapping is compatible with the 64-bit MAC.

  • Lane 0 data: xgmii_rx[7:0]
  • Lane 0 control: xgmii_rx[8]
  • Lane 1 data: xgmii_rx[16:9]
  • Lane 1 control: xgmii_rx[17]
  • Lane 2 data: xgmii_rx[25:18]
  • Lane 2 control: xgmii_rx[26]
  • Lane 3 data: xgmii_rx[34:27]
  • Lane 3 control: xgmii_rx[35]
  • Lane 4 data: xgmii_rx[43:36]
  • Lane 4 control: xgmii_rx[44]
  • Lane 5 data: xgmii_rx[52:45]
  • Lane 5 control: xgmii_rx[53]
  • Lane 6 data: xgmii_rx[61:54]
  • Lane 6 control: xgmii_rx[62]
  • Lane 7 data: xgmii_rx[70:63]
  • Lane 7 control: xgmii_rx[71]
link_fault_status_xgmii_rx_data[] — Out 2 The following values indicate the link fault status:
  • 0x0 = No link fault
  • 0x1 = Local fault
  • 0x2 = Remote fault
Level Two Title