Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 683426
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

5.8. RX Configuration and Status Registers

Table 29.  RX Configuration and Status Registers
Word Offset Register Name Description Access HW Reset Value
0x00A0 rx_transfer_control
  • Bit 0—RX path enable.

    0: Enables the RX path.

    1: Disables the RX path. The MAC IP core drops all incoming frames.

  • Bits 31:1—reserved.

A change of value in this register takes effect at a packet boundary. Any transfer in progress is not affected.

RW 0x0
0x00A2 rx_transfer_status

The MAC sets the following bits to indicate the status of the RX datapath.

  • Bits 7:0—reserved.
  • Bit 8: RX datapath status.

    0: The RX datapath is idle.

    1: An RX data transfer is in progress.

  • Bits 11:9—reserved.
  • Bit 12: RX datapath reset status.

    0: The RX datapath is not in reset.

    1: The RX datapath is in reset.

 RO 0x0
0x00A4 rx_padcrc_control
  • Bits [1:0]—Padding and CRC removal on receive.

    00: Retains the padding bytes and CRC field, and forwards them to the client.

    01: Retains only the padding bytes. The MAC IP core removes the CRC field before it forwards the RX frame to the client.

    11: Removes the padding bytes and CRC field before the RX frame is forwarded to the client.

    10: Reserved.

  • Bits 31:2—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x1
0x00A6 rx_crccheck_control CRC checking on receive.
  • Bit 0—always set this bit to 0.
  • Bit 1—CRC checking enable.

    0: Ignores the CRC field.

    1: Checks the CRC field and reports the status to avalon_st_rx_error[1] and avalon_st_rxstatus_error.

  • Bits 31:2—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x2
0x00A8 rx_custom_preamble_forward 10
  • Bit 0—configures the forwarding of the custom preamble to the client.

    0: Removes the custom preamble from the RX frame.

    1: Retains and forwards the custom preamble to the client.

  • Bits 31:1—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x0
0x00AA rx_preamble_control 10
  • Bit 0—preamble passthrough enable on receive.

    0: Disables preamble passthrough. The MAC IP core checks for START and SFD during packet decapsulation process.

    1: Enables preamble passthrough. The MAC IP core checks only for START during packet decapsulation process.

  • Bits 31:1—reserved.

Configure this register before you enable the MAC IP core for operations.

RW 0x0
0x00AC rx_frame_control

Configure this register before you enable the MAC IP core for operations.

RW 0x3
Bit 0—EN_ALLUCAST

0: Filters RX unicast frames using the primary MAC address. The MAC IP core drops unicast frames with a destination address other than the primary MAC address.

1: Accepts all RX unicast frames.

Setting this bit and the EN_ALLMCAST to 1 puts the MAC IP core in the promiscuous mode.

Bit 1—EN_ALLMCAST

0: Drops all RX multicast frames.

1: Accepts all RX multicast frames.

Setting this bit and the EN_ALLUCAST bit to 1 is equivalent to setting the MAC IP core to the promiscuous mode.

Bit 2—reserved.
Bit 3—FWD_CONTROL. When you turn on the Priority-based Flow Control parameter, this bit affects all control frames except the IEEE 802.3 pause frames and priority-based control frames. When the Priority-based Flow Control parameter is not enabled, this bit affects all control frames except the IEEE 802.3 pause frames.

0: Drops the control frames.

1: Forwards the control frames to the client.

Bit 4—FWD_PAUSE

0: Drops pause frames.

1: Forwards pause frames to the client.

Bit 5—IGNORE_PAUSE

0: Processes pause frames.

1: Ignores pause frames.

Bits 15:6—reserved.
Bit 16—EN_SUPP0

0: Disables the use of supplementary address 0.

1: Enables the use of supplementary address 0.

Bit 17—EN_SUPP1

0: Disables the use of supplementary address 1.

1: Enables the use of supplementary address 1.

Bit 18—EN_SUPP2

0: Disables the use of supplementary address 2.

1: Enables the use of supplementary address 2.

Bit 19—EN_SUPP3

0: Disables the use of supplementary address 3.

1: Enables the use of supplementary address 3.

Bits 31:20—reserved.
0x00AE rx_frame_maxlength
  • Bits 15:0—specify the maximum allowable frame length. The MAC asserts the avalon_st_rx_error[3] signal when the length of the RX frame exceeds the value of this register.
  • Bits 16:31—reserved.
Configure this register before you enable the MAC IP core for operations. 		RW 1518
0x00AF rx_vlan_detection
  • Bit 0—RX VLAN detection disable.

    0: The MAC detects VLAN and stacked VLAN frames.

    1: The MAC does not detect VLAN and stacked VLAN frames. When received, the MAC treats them as basic frames and considers their tags as payload bytes.

  • Bits 31:1—reserved.
 RW 0x0
0x00B0 rx_frame_spaddr0_0 You can specify up to four 6-byte supplementary addresses:
  • rx_framedecoder_spaddr0_0/1
  • rx_framedecoder_spaddr1_0/1
  • rx_framedecoder_spaddr2_0/1
  • rx_framedecoder_spaddr3_0/1
Configure the supplementary addresses before you enable the MAC RX datapath. Map the supplementary addresses to the respective registers in the same manner as the primary MAC address. Refer to the description of primary_mac_addr0 and primary_mac__addr1.The MAC IP core uses the supplementary addresses to filter unicast frames when the following conditions are set:
  • The use of the supplementary addresses are enabled using the respective bits in the rx_frame_control register.
  • The en_allucast bit of the rx_frame_control register is set to 0.
RW 0x0
0x00B1 rx_frame_spaddr0_1
0x00B2 rx_frame_spaddr1_0
0x00B3 rx_frame_spaddr1_1
0x00B4 rx_frame_spaddr2_0
0x00B5 rx_frame_spaddr2_1
0x00B6 rx_frame_spaddr3_0
0x00B7 rx_frame_spaddr3_1
0x00C0 rx_pfc_control 11
  • Bits 7:0—enables priority-based flow control on the RX datapath. Setting bit n to 0 enables priority-based flow control for priority queue n. For example, setting rx_pfc_control[0] to 0 enables queue 0.
  • Bits 15:9—reserved.
  • Bit 16—configures the forwarding of priority-based control frames to the client.

    0: Drops the control frames.

    1: Forwards the control frames to the client.

  • Bits 31:17—reserved.
Configure this register before you enable the MAC IP core for operations. 		RW

0x1
0x00FC rx_pktovrflow_error 36-bit error counter that collects the number of RX frames that are truncated when a FIFO buffer overflow persists:
  • 0x00FC = Lower 32 bits of the error counter.
  • 0x00FD = Upper 4 bits of the error counter occupy bits [3:0]. Bits [31:4] are unused.

To read the counter, read the lower 32 bits followed by the upper 4 bits. The IP core clears the counter after a read.

 RO 0x0
0x00FD
0x00FE rx_pktovrflow_etherStatsDropEvents 36-bit error counter that collects the number of RX frames that are dropped when FIFO buffer overflow persists:
  • 0x00FE = Lower 32 bits of the error counter.
  • 0x00FF = Upper 4 bits of the error counter occupy bits [3:0]. Bits [31:4] are unused.

To read the counter, read the lower 32 bits followed by the upper 4 bits. The IP core clears the counter after a read.

 RO 0x0
0x00FF
Related Information
10 This register is used only when you turn on the Enable preamble pass-through mode option. It is reserved when not used.
11 This register is used only when you turn on the Enable priority-based flow control (PFC) option. It is reserved when not used.
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