Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

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ID 683417
Date 10/29/2021
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Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines x
Intel® Cyclone® 10 GX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices Document Revision History for the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines
Intel® Cyclone® 10 GX Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface Pins Voltage Sensor Pins Reference Pins Supply Pins Transceiver Pins Notes to Intel® Cyclone® 10 GX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Cyclone® 10 GX Devices x
Example 1— Intel® Cyclone® 10 GX Example 2— Intel® Cyclone® 10 GX
Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines

Dedicated Configuration/JTAG Pins

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 2.  Dedicated Configuration/JTAG Pins
Pin Name Pin Functions Pin Description Connection Guidelines
nIO_PULLUP Input

Dedicated input pin that determines the internal pull-ups on user I/O pins and dual-purpose I/O pins (DATA[0:31], CLKUSR, INIT_DONE, DEV_OE, and DEV_CLRn) are on or off before and during configuration.

A logic high turns off the weak pull-up, while a logic low turns on the weak pull-up.

Tie the nIO-PULLUP pin directly to VCC using a 1 kΩ pull-up resistor, or directly to GND. This pin has an internal 25-kΩ pull-down.

If you tie this pin to VCC, ensure all user I/O pins and dual-purpose I/O pins are at logic–0 before and during configuration.

TEMPDIODEp Input Pin used for temperature sensing diode (bias-high input) inside the FPGA. If you do not use the temperature sensing diode with an external temperature sensing device, connect this pin to GND.
TEMPDIODEn Input Pin used for temperature sensing diode (bias-low input) inside the FPGA. If you do not use the temperature sensing diode with an external temperature sensing device, connect this pin to GND.
MSEL[0:2] Input Configuration input pins that set the configuration scheme for the FPGA device.

These pins are internally connected through a 25-kΩ resistor to GND. Do not leave these pins floating. When these pins are unused, connect them to GND.

Depending on the configuration scheme used, tie these pins to VCCPGM or GND. For more information about the configuration scheme options, refer to the Configuration, Design Security, and Remote System Upgrades for Intel® Cyclone® 10 GX Devices chapter.

If you use JTAG configuration scheme, connect these pins to GND.

nCE Input Dedicated active-low chip enable pin. When the nCE pin is low, the device is enabled. When the nCE pin is high, the device is disabled.

In multi-device configuration, the nCE pin of the first device is tied low while its nCEO pin drives the nCE pin of the next device in the chain.

In single-device configuration and JTAG programming, connect the nCE pin to GND.

nCONFIG Input Dedicated configuration control input pin. Pulling this pin low during user mode causes the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level initiates reconfiguration.

Connect the nCONFIG pin directly to the configuration controller when the FPGA uses a passive configuration scheme.

Connect the nCONFIG pin through a 10-kΩ resistor tied to VCCPGM when the FPGA uses an active serial (AS) configuration scheme.

If you do not use this pin, connect the pin directly or through a 10-kΩ resistor to VCCPGM.

CONF_DONE Bidirectional (open-drain)

Dedicated configuration done pin.

As a status output, the CONF_DONE pin drives low before and during configuration. After all configuration data is received without error and the initialization cycle starts, CONF_DONE is released.

As a status input, the CONF_DONE pin goes high after all data is received. Then the device initializes and enters user mode. This pin is not available as a user I/O pin.

Connect an external 10-kΩ pull-up resistors to VCCPGM. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host.

When you use passive configuration schemes, the configuration controller monitors this pin.

nCEO I/O, Output (open-drain)

When device configuration is complete, the nCEO pin drives low.

If you do not use this pin as a configuration pin, you can use this pin as a user I/O pin.

In multi-device configuration, the nCEO pin feeds the nCE pin of a subsequent FPGA.

Connect this pin through an external 10-kΩ pull-up resistor to VCCPGM.

In single-device configuration, you can leave this pin floating.

nSTATUS Bidirectional (open-drain)

Dedicated configuration status pin. The FPGA drives the nSTATUS pin low immediately after power-up, and releases the pin after power-on reset (POR) time.

As a status output, the nSTATUS pin is pulled low if an error occurs during configuration.

As a status input, the device enters an error state when the nSTATUS pin is driven low by an external source during configuration or initialization. This pin is not available as a user I/O pin.

Connect an external 10-kΩ pull-up resistors to VCCPGM. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host.

When you use passive configuration schemes, the configuration controller monitors this pin.

TCK Input Dedicated JTAG test clock input pin.

Connect this pin through a 1-kΩ pull-down resistor to GND. This pin has an internal 25-kΩ pull-down.

Do not drive voltage higher than 1.8-, 1.5-, or 1.2-V VCCPGM supply for the TCK pin. The TCK input pin is powered by the VCCPGM supply.

TMS Input Dedicated JTAG test mode select input pin.

Connect this pin through a 1–10-kΩ pull-up resistor to VCCPGM.

If the JTAG interface is not used, connect the TMS pin to VCCPGM using a 1-kΩ resistor. This pin has an internal 25-kΩ pull-up.

Do not drive voltage higher than 1.8-, 1.5-, or 1.2-V VCCPGM supply for the TMS pin. The TMS input pin is powered by the VCCPGM supply.

TDI Input Dedicated JTAG test data input pin.

Connect this pin through a 1–10-kΩ pull-up resistor to VCCPGM.

If the JTAG interface is not used, connect the TDI pin to VCCPGM using a 1-kΩ resistor. This pin has an internal 25-kΩ pull-up.

Do not drive voltage higher than 1.8-, 1.5-, or 1.2-V VCCPGM supply for the TDI pin. The TDI input pin is powered by the VCCPGM supply.

TDO Output Dedicated JTAG test data output pin. If the JTAG interface is not used, leave the TDO pin unconnected.
TRST Input Dedicated active low JTAG test reset input pin. The TRST pin is used to asynchronously reset the JTAG boundary-scan circuit.

Utilization of the TRST pin is optional. If you do not use this pin, tie this pin through a 1-kΩ pull-up resistor to VCCPGM.

When you use this pin, ensure that the TMS pin is held high or the TCK pin is static when the TRST pin is changing from low to high.

To disable the JTAG circuitry, tie this pin to GND. This pin has an internal 25-kΩ pull-up.

Do not drive voltage higher than 1.8-, 1.5-, or 1.2-V VCCPGM supply for the TRST pin. The TRST input pin is powered by the VCCPGM supply.

nCSO[0:2] Output Dedicated output control signal from the FPGA to the EPCQ-L device in AS configuration scheme that enables the EPCQ-L device. When you are not programming the FPGA in the AS configuration scheme, the nCSO pin is not used. When you do not use this pin as an output pin, leave this pin unconnected.
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