Intel® FPGA Streaming Video Protocol Specification

ID 683397
Date 5/15/2024
Public
Document Table of Contents

2.2.4. YCbCr 422 Pixel Packing

The Intel FPGA streaming video protocol specifies a packing scheme for YCbCr 422 pixels.
Note: YCbCr 422 video packets must be an even number of pixels in length to ensure complete pairs of chroma information are transported.
Figure 22. 8 bit YCbCr 422 video packet 1PIPThe figure shows for 8 bit YCbCr video, TDATA is 16 bits wide, which is the minimum protocol width.
Figure 23. 10 bit YCbCr 422 video packet 4 PIPIn this figure, each pixel comprises a Y (luma) value and a chroma value (either blue or red). Ten bits per symbol requires four bits of padding between pixels so that each pixel (luma and chroma pair) aligns with a byte boundary
Figure 24. 12 bit YCbCr 422 video packet 2 PIPIn this figure, each pixel comprises a Y (luma) value and a chroma value (either blue or red). Twelve bits per symbol gives a packing that aligns each pixel with a byte boundary so requiring no additional padding..