Qsys System Design Tutorial

ID 683378
Date 5/04/2015
Public
Document Table of Contents

1.5.1. Create the Hierarchical Memory Tester System

The memory tester system includes several slave interfaces. However, the memory tester groups the interfaces behind a pipeline bridge that exports a single slave interface to the top-level system. This technique allows the top-level system to access all of the memory-mapped slave ports by reading and writing to a single pipeline bridge slave interface. The bridge also adds a level of pipelining, which can improve timing performance.
Memory Tester Design Interface


  1. In Qsys, create a new system called, memory_tester_system.
  2. For the clk instance, turn off Clock frequency is known to indicate that the higher-level hierarchical system that instantiates this subsystem provides the clock frequency.
  3. In the IP Catalog, select the Avalon-MM Pipeline Bridge to add to your Qsys system.
  4. For the Avalon-MM Pipeline Bridge, in the parameter editor, type 13 for the Address width.
    To accommodate for the address translation from master to slave, that is a byte address as the input, and a word address (4 bytes) as the output, the address width increases from 11.
  5. Rename the instance to mm_bridge.
  6. Set the mm_bridge_clk interface to clk_0.
  7. Export the mm_bridge s0 interface with the name slave.