AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

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ID 683343
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY x
Features Requirements Design Example Walkthrough Components Parameters Design Example Testbench Clocking Scheme Reset Scheme Interface Signals Register Map Document Revision History for Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
Design Example Walkthrough x
Setting Up the Design Examples Changing Number of Channels Configuring PHY Speed IP Regeneration
Configuring PHY Speed x
Changing Speed between 10G and 1G in 1000BaseX mode Changing Speed between 1G, 100M, and 10M SGMII
Design Example Testbench x
Testbench Components Testbench Files Simulating Testbench Test Case
Simulating Testbench x
Using ModelSim Simulator Using VCS Simulator
Test Case x
Test Scenario for Design Example without IEEE 1588v2 Test Scenario for Design Example with IEEE 1588v2
Clocking Scheme x
Clocking Diagram Sync-E Support
Sync-E Support x
Enable Ref Clock Sharing Disable Ref Clock Sharing
Reset Scheme x
Design Example without IEEE 1588v2 Design Example with IEEE 1588v2
Design Example without IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Design Example with IEEE 1588v2 x
Multi Channel Level Reset Scheme Channel Level Reset Scheme
Interface Signals x
Clock and Reset Interface Signals Avalon-MM Interface Signals Avalon-ST Interface Signals PHY Interface Signals MDIO Interface Signals IEEE 1588v2 Timestamp Interface Signals Packet Classifier Interface Signals ToD Interface Signals
Register Map x
Master TOD 1G TOD 10G TOD PHY 1G/10G MAC
Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

IP Regeneration

Regeneration of IP files is required when upgrading to a new version of ACDS. This process involves 2 different tools: Platform Designer and IP Catalog. The following table shows the IPs that need regeneration and the tools involved.

Table 3.  IP Requires Regeneration
IP Tools IP File Locations
address_decoder_channel Platform Designer ADDRESS_DECODER/address_decoder_channel.qsys
address_decoder_multi_channel Platform Designer ADDRESS_DECODER/address_decoder_multi_channel.qsys
altera_eth_10g_mac IP Catalog MAC_NO_1588/altera_eth_10g_mac.qsys
altera_eth_10gkr_phy IP Catalog PHY_NO_1588/altera_eth_10gkr_phy.qsys
altera_xcvr_reset_controller IP Catalog XCVR_RESET_CONTROLLER/altera_xcvr_reset_controller.qsys
nf_xcvr_10g_pll IP Catalog nf_atx_pll/nf_xcvr_10g_pll.qsys
nf_xcvr_1g_pll IP Catalog nf_xcvr_fpll/nf_xcvr_1g_pll.qsys
pll IP Catalog PLL/pll.qsys
pll_2
Note: This IP is only available for design example with IEEE 1588v2.
IP Catalog PLL/pll_2.qsys

Launch the tool and open the IP files listed in the table to regenerate the IP.

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