AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY

ID 683343
Date 11/06/2017
Public
Document Table of Contents

Avalon-ST Interface Signals

The following table lists the Avalon-ST interface signals. These interface signals are applicable to both design examples.

Table 8.   Avalon-ST Interface Signals
Signal Direction Width Description
avalon_st_tx_startofpacket[] input [NUM_CHANNELS] Assert this signal to mark the beginning of the transmit data on the Avalon-ST interface.
avalon_st_tx_endofpacket[] input [NUM_CHANNELS] Assert this signal to mark the end of the transmit data on the Avalon-ST interface.
avalon_st_tx_valid[] input [NUM_CHANNELS] Assert this signal to indicate that avalon_st_tx_data[] and other signals on this interface are valid.
avalon_st_tx_ready[] output [NUM_CHANNELS] When asserted, this signal indicates that the MAC IP core is ready to accept data.
avalon_st_tx_error[][] input [NUM_CHANNELS][64] Assert this signal to indicate the current transmit packet contains errors.
avalon_st_tx_data[][] input [NUM_CHANNELS][3] Carries the transmit data from the client.
avalon_st_tx_empty[] input [NUM_CHANNELS] Use this signal to specify the number of bytes that are empty (not used) during cycles that contain the end of a packet.

0x0=All bytes are valid.

0x1=The last byte is invalid.

0x2=The last two bytes are invalid.

0x3=The last three bytes are invalid.

avalon_st_rx_startofpacket[] output [NUM_CHANNELS] When asserted, this signal marks the beginning of the receive data on the Avalon-ST interface.
avalon_st_rx_endofpacket[] output [NUM_CHANNELS] When asserted, this signal marks the end of the receive data on the Avalon-ST interface.
avalon_st_rx_valid[] output [NUM_CHANNELS] When asserted, this signal indicates that avalon_st_rx_data[]and other signals on this interface are valid.
avalon_st_rx_ready[] input [NUM_CHANNELS] Assert this signal when the client is ready to accept data.
avalon_st_rx_error[][] output [NUM_CHANNELS][64] When set to 1, the respective bits indicate an error type:
  • Bit 0—PHY error. For 10 Gbps, the data on xgmii_rx_data contains a control error character (FE). For 10 Mbps,100 Mbps,1 Gbps, gmii_rx_err or mii_rx_err is asserted.
  • Bit 1—CRC error. The computed CRC value differs from the received CRC.
  • Bit 2—Undersized frame. The receive frame length is less than 64 bytes.
  • Bit 3—Oversized frame. The receive frame length is more than MAX_FRAME_SIZE.
  • Bit 4—Payload length error. The actual frame payload length is different from the value in the length/type field.
  • Bit 5—Overflow error. The receive FIFO buffer is full while it is still receiving data from the MAC IP core.
avalon_st_rx_data[][] output [NUM_CHANNELS][3] Carries the receive data to the client.
avalon_st_rx_empty[][] output [NUM_CHANNELS][6] Contains the number of bytes that are empty (not used) during cycles that contain the end of a packet.
avalon_st_tx_status_valid[] output [NUM_CHANNELS] When asserted, this signal qualifies avalon_st_txstatus_data[] and avalon_st_txstatus_error[].
avalon_st_tx_status_data[][] output [NUM_CHANNELS][40] Contains information about the transmit frame.
  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_tx_status_error[][] output [NUM_CHANNELS][7] When set to 1, the respective bit indicates the following error type in the receive frame.
  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.
The error status is invalid when an overflow occurs.
avalon_st_rxstatus_valid[] output [NUM_CHANNELS] When asserted, this signal qualifies avalon_st_txstatus_data[] and avalon_st_txstatus_error[]. The MAC IP core asserts this signal in the same clock cycle avalon_st_rx_endofpacket is asserted.
avalon_st_rxstatus_data[][] output [NUM_CHANNELS][40] Contains information about the transmit frame.
  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_rxstatus_error[][] output [NUM_CHANNELS][7] When set to 1, the respective bit indicates the following error type in the receive frame.
  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.
The error status is invalid when an overflow occurs.
avalon_st_pause_data[][] input [NUM_CHANNELS][2] Set this signal to the following values to trigger the corresponding actions.
  • 0x0: Stops pause frame generation.
  • 0x1: Generates an XON pause frame.
  • 0x2: Generates an XOFF pause frame. The MAC IP core sets the pause quanta field in the pause frame to the value in the tx_pauseframe_quanta register.
  • 0x3: Reserved.
Note: This signal only takes effect if tx_pauseframe_enable[2:1] is 00 (default)