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1.1. Features
1.2. Overview
1.3. Programming Single and Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core
1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software
1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software
1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer
1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
1.8. Intel® FPGA Serial Flash Loader IP Core Parameter
1.9. Intel® FPGA Serial Flash Loader IP Core Signals
1.10. Document Revision History for AN 370: Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
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1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer
You can use the Intel® Quartus® Prime programmer to generate serial configuration device programming files. The Intel® Quartus® Prime programmer can generate both .jic and .jam files with the factory default enhanced SFL image that is run directly from the Intel® Quartus® Prime programmer.
As long as the JTAG interface of the FPGA is accessible for programming, you can use the factory default enhanced SFL image that is run directly from the Intel® Quartus® Prime programmer for your application. If you enable tamper protection in design security feature, JTAG configuration is disabled. However, the serial configuration device is still accessible from JTAG interface if the FPGA is configured with encrypted configuration image that contains Intel® FPGA Serial Flash Loader IP core.