DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Public
Document Table of Contents

6.6.4. Video Interface

This interface (rxN_video_out) allows access to the video data as a non-Avalon-ST stream. You can use this stream to interface with an external pixel clock recovery function. The stream provides synchronization pulses at the start and end of active lines, and at the start and end of active frames.

Figure 36. Video Out Image Port Timing Diagram

The rxN_vid_overflow signal is always valid, regardless of the logical state of rxN_vid_valid. rxN_vid_overflow is asserted for at least one clock cycle when the sink core internal video data FIFO runs into an overflow condition. This condition can occur when the rxN_vid_clk frequency is too low to transport the received video data successfully.

Specify the maximum data color depth in the DisplayPort parameter editor. The same output port transfers both RGB and YCbCr data in 4:4:4, 4:2:2, or 4:2:0 color format. Data is most-significant bit aligned and formatted for 4:4:4.

Figure 37. Video Output Data Format18 bpp to 48 bpp for RGB/YCbCr 4:4:4, 16 bpp to 32 bpp for YCbCr 4:2:2, and 12 bpp to 24 bpp for YCbCr 4:2:0 port width when rxN_video_out port width is 48 (Maximum video output color depth = 16 bpc, Pixel output mode = Single)
Table 53.  Video Ports for 4:2:2 and 4:2:0 Color Formats
Color Format Description
Sub-sampled 4:2:2 color format
  • Video port bits 47:32 are unused
  • Video port bits 31:16 always transfer the Y component
  • Video port bits 15:0 always transfer the alternate Cb or Cr component
Sub-sampled 4:2:0 color format
  • For even lines (starting with line 0)
    • Video port bits 47:32 always transfer the Yn+1 component.
    • Video port bits 31:16 always transfer the Yn component.
    • Video port bits 15:0 always transfer the Cbn component.
  • For odd lines
    • Video port bits 47:32 always transfer the Yn+1 component.
    • Video port bits 31:16 always transfer the Yn component.
    • Video port bits 15:0 always transfer the Crn component.
Table 54.  YCbCr 4:2:0 Input Data Ordering Compared to RGB 4:4:4
Pixel Indexes R Position G Position B Position

0 and 1

Y1

Y0

  • Cb0 (Even lines)
  • Cr0 (Odd lines)

2 and 3

Y3

Y2

  • Cb2 (Even lines)
  • Cr2 (Odd lines)

4 and 5

Y5

Y4

  • Cb4 (Even lines)
  • Cr4 (Odd lines)
... ... ... ...

If you set Pixel output mode to Dual or Quad, the IP produces two or four pixels in parallel, respectively. To support video resolutions with horizontal active, front and pack porches with lengths that are not divisible by two or four, rxN_vid_valid is widened. For example, for two pixels per clock, rxN_vid_valid[0] is asserted when pixel N belongs to active video and rxN_vid_valid[1] is asserted when pixel n + 1 belongs to active video.

The following figure shows the pixel data order from the least significant bits to the most significant bits.

Figure 38. Video Output AlignmentFor RGB 18 bpp when rxN_video_out port width is 96 (Maximum video output color depth = 8 bpc, Pixel output mode = Quad))