Nios II Custom Instruction User Guide

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ID 683242
Date 4/27/2020
Public
Document Table of Contents
Document Table of Contents x
1. Nios II Custom Instruction Overview 2. Custom Instruction Hardware Interface 3. Custom Instruction Software Interface 4. Design Example: Cyclic Redundancy Check 5. Introduction to Nios® II Floating Point Custom Instructions 6. Nios II Floating Point Hardware 2 Component 7. Nios® II Floating Point Hardware (FPH1) Component 8. Document Revision History for Nios II Custom Instruction User Guide
1. Nios II Custom Instruction Overview x
1.1. Custom Instruction Implementation
1.1. Custom Instruction Implementation x
1.1.1. Custom Instruction Hardware Implementation 1.1.2. Custom Instruction Software Implementation
2. Custom Instruction Hardware Interface x
2.1. Custom Instruction Types
2.1. Custom Instruction Types x
2.1.1. Combinational Custom Instructions 2.1.2. Multicycle Custom Instructions 2.1.3. Extended Custom Instructions 2.1.4. Internal Register File Custom Instructions 2.1.5. External Interface Custom Instructions
2.1.1. Combinational Custom Instructions x
2.1.1.1. Combinational Custom Instruction Ports 2.1.1.2. Combinational Custom Instruction Timing
2.1.2. Multicycle Custom Instructions x
2.1.2.1. Multicycle Custom Instruction Ports 2.1.2.2. Multicycle Custom Instruction Timing
2.1.3. Extended Custom Instructions x
2.1.3.1. Extended Custom Instruction Timing
2.1.4. Internal Register File Custom Instructions x
2.1.4.1. Internal Register File Custom Instruction Example 2.1.4.2. Internal Register File Custom Instruction Ports
3. Custom Instruction Software Interface x
3.1. Custom Instruction Software Examples 3.2. Built-in Functions and User-defined Macros 3.3. Custom Instruction Assembly Language Interface
3.2. Built-in Functions and User-defined Macros x
3.2.1. Built-in Functions with No Return Value 3.2.2. Built-in Functions that Return a Value of Type Int 3.2.3. Built-in Functions that Return a Value of Type Float 3.2.4. Built-in Functions that Return a Pointer Value
3.3. Custom Instruction Assembly Language Interface x
3.3.1. Custom Instruction Assembly Language Syntax 3.3.2. Custom Instruction Assembly Language Examples 3.3.3. Custom Instruction Word Format
3.3.3. Custom Instruction Word Format x
3.3.3.1. Select Index Field (N)
4. Design Example: Cyclic Redundancy Check x
4.1. Building the CRC Example Hardware 4.2. Building the CRC Example Software
4.1. Building the CRC Example Hardware x
4.1.1. Setting up the Environment for the CRC Example Design 4.1.2. Opening the Component Editor 4.1.3. Specifying the Custom Instruction Component Type 4.1.4. Displaying the Custom Instruction Block Symbol 4.1.5. Adding the CRC Custom Instruction HDL Files 4.1.6. Configuring the Custom Instruction Parameter Type 4.1.7. Setting Up the CRC Custom Instruction Interfaces 4.1.8. Configuring the Custom Instruction Signal Type 4.1.9. Saving and Adding the CRC Custom Instruction 4.1.10. Generating and Compiling the CRC Example System
4.1.7. Setting Up the CRC Custom Instruction Interfaces x
4.1.7.1. Specifying Additional Interfaces
4.2. Building the CRC Example Software x
4.2.1. Running and Analyzing the CRC Example Software 4.2.2. Using the User-defined Custom Instruction Macro
4.2.1. Running and Analyzing the CRC Example Software x
4.2.1.1. Output of the CRC Design Example Software Run on a Cyclone V E FPGA Development Kit using the Intel® Quartus® Prime Software v15.1.
5. Introduction to Nios® II Floating Point Custom Instructions x
5.1. Floating Point Background 5.2. IEEE 754 Format 5.3. Rounding Schemes 5.4. Special Floating Point Cases
5.2. IEEE 754 Format x
5.2.1. Unit in the Last Place 5.2.2. Floating Point Value Encoding
5.3. Rounding Schemes x
5.3.1. Nearest Rounding 5.3.2. Truncation Rounding 5.3.3. Faithful Rounding 5.3.4. Rounding Examples
6. Nios II Floating Point Hardware 2 Component x
6.1. Overview of the Floating Point Hardware 2 Component 6.2. Floating Point Hardware 2 IEEE 754 Compliance 6.3. IEEE 754 Exception Conditions with FPH2 6.4. Floating Point Hardware 2 Operations 6.5. Building the FPH2 Example Hardware 6.6. Building the FPH2 Example Software 6.7. FPH2 Implementation of GCC Options 6.8. Nios II FPH2 and the Newlib Library 6.9. C Macros for round(), fmins(), and fmaxs()
6.6. Building the FPH2 Example Software x
6.6.1. FPH2 and Nios II GCC 6.6.2. Floating Point Hardware 2 Conversions 6.6.3. Nios II FPH2 Software Options
6.6.3. Nios II FPH2 Software Options x
6.6.3.1. -mcustom-<operation> 6.6.3.2. Nios II FPH2 Pragmas 6.6.3.3. -mcustom-fpu-cfg
6.7. FPH2 Implementation of GCC Options x
6.7.1. -fno-math-errno 6.7.2. -fsingle-precision-constant 6.7.3. -funsafe-math-optimizations 6.7.4. -ffinite-math-only 6.7.5. -fno-trapping-math 6.7.6. -frounding-math
7. Nios® II Floating Point Hardware (FPH1) Component x
7.1. Creating the FPH1 Example Hardware 7.2. Adding FPH1 to the Design and Configuring the Device 7.3. Building the FPH1 Example Software 7.4. Nios II FPH1 and the Newlib Library 7.5. Assessing Your Floating Point Optimization Needs 7.6. Hardware Divide Considerations with FPH1
7.3. Building the FPH1 Example Software x
7.3.1. Creating the FPH1 Software Project 7.3.2. Running and Analyzing the FPH1 Example Software 7.3.3. Software Implementation for FPH1
1. Nios II Custom Instruction Overview
2. Custom Instruction Hardware Interface
3. Custom Instruction Software Interface
4. Design Example: Cyclic Redundancy Check
5. Introduction to Nios® II Floating Point Custom Instructions
6. Nios II Floating Point Hardware 2 Component
7. Nios® II Floating Point Hardware (FPH1) Component
8. Document Revision History for Nios II Custom Instruction User Guide

5.2. IEEE 754 Format

The figure below shows the fields in an IEEE 754 32-bit single-precision value. The table below provides a description of the fields. Normal single-precision floating point numbers have the value (-1) S * 1.FRAC * 2 EXP -127 .
Figure 20. Single-Precision Format
Table 9.  Single-Precision Field Descriptions
Mnemonic Name Description
FRAC Fraction Specifies the fractional portion (right of the binary point) of the mantissa. The integer value (left of the binary point) is always assumed to be 1 for normal values so it is omitted. This omitted value is called the hidden bit. The mantissa ranges from ≥1.0 to <2.0.
EXP Biased Exponent Contains the exponent biased by the value 127. The biased exponent value 0x0 is reserved for zero and subnormal values. The biased exponent value 0xff is reserved for infinity and NaN. The biased exponent ranges from 1 to 0xfe for normal numbers (-126 to 127 when the bias is subtracted out).
S Sign Specifies the sign. 1 = negative, 0 = positive. Normal values, zero, infinity, and subnormals are all signed. NaN has no sign, so the S field is ignored.
The IEEE 754 standard provides the following special values:
  • Zero (EXP=0, FRAC=0)
  • Subnormal (EXP=0, FRAC≠0)
  • Infinity (EXP=255, FRAC=0)
  • NaN (EXP=255, FRAC≠0)
Note: Zero, subnormal, and infinity are signed as specified by the S field. NaN has no sign so the S field is ignored.

Section Content
Unit in the Last Place
Floating Point Value Encoding

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