SDI II Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683209
Date 12/09/2022
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
1.6. SDI II Intel® FPGA Design Example Parameters x
1.6.1. Design Example Presets
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

4. Revision History for SDI II Intel® Arria® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.12.09 22.4 Added four design example presets to the Parameter Editor.
2022.03.28 21.4 Updated Select Design parameter description for Parallel loopback without external VCXO in SDI II Intel FPGA Design Example Parameters for Intel Aria 10 Devices table.
2021.10.08 21.3
  • Removed NCSim from the following figure and tables:
    • Figure: Directory Structure for the Design Examples.
    • Table: Other Generated Files in Simulation Folder.
    • Table: Steps to Run Simulation
  • Edited the list of Software in Hardware and Software Requirements:
    • Changed ModelSim* - Intel® FPGA Edition to Questa* Intel® FPGA Edition .
    • Changed ModelSim* - Intel® FPGA Starter Edition to ModelSim SE* .
2021.08.27 18.1
  • Changed from Streams Interleaved to Multiplex Type to align with SMPTE spec for below:
    • RX/TX/DU Top Signals Table for rx_vid_std, tx_vid_std and sdi_tx_ln_b signals.
    • On-board User LED Functions Table.
    • Figure Sequence of Video Standards for Triple-Rate and Multi-Rate Designs.
    • Description in Simulation Testbench for single-rate and multi-rate designs.
2020.01.29 18.1 Edited the description for the tx_pll_refclk_sel signal in the Interface Signals section to include information about the dynamic switching feature.
2018.11.20 18.1
  • Updated the Directory Structure section with new folders and files for loopback design and simulation:
    • rcfg_pll_frac.v
    • modelsim_files.tcl
    • ncsim_files.tcl
    • riviera_files.tcl
    • vcs_files.tcl
    • vcsmx_files.tcl
    • xcelium_files.tcl
    • tb_ln_check.v
    • cds.lib
    • hdl.var
    • xcelium_setup.sh
    • xcelium_sim.sh
  • Added a note that fPLL is only available when you select the Parallel loopback without external VCXO design.
  • Added information that the multi-rate designs support rx_coreclk frequency of 297 MHz.
  • Added a step in the Compiling and Testing the Design section to set the frequency for CLK1 in the Si5338 (U14) tab of the Clock Control GUI to 297 MHz if you set the Rx core clock (rx_coreclk) Frequency parameter to 297.0/296.70 MHz.
  • Added instructions to run simulation using the Xcelium Parallel Simulator in the Simulating the Design section.
  • Edited the Hardware and Software Requirements section to include the Xcelium Parallel simulator.
  • Added a 625-MHz dedicated transceiver clock signal (refclk_fmca_p) in the Interface Signals section.
  • Added Upgrading Your Design section to provide guidelines about upgrading your existing designs to the latest version.
  • Added information about the simplex receiver channel calibration issue and a KDB link about the issue in the Design Considerations section.
Date Version Changes
May 2017 2017.05.08
  • Rebranded as Intel.
  • Changed the part number.
  • Updated information about the parallel design examples and added new information about the serial design example.
  • Added files designated for Intel® Quartus® Prime Pro Edition.
  • Added information about video pattern generator interface signals and parameters.
  • Added link to archived version of the Arria 10 SDI II IP Core Design Example User Guide.
October 2016 2016.10.31 Initial release.
Level Two Title