Visible to Intel only — GUID: sss1438255014442
Ixiasoft
1. Intel® Stratix® 10 Overview
2. Intel® Stratix® 10 JTAG BST Architecture
3. Intel® Stratix® 10 BST Operation Control
4. Intel® Stratix® 10 I/O Voltage for JTAG Operation
5. Performing Intel® Stratix® 10 Boundary-Scan Testing
6. Enabling and Disabling Intel® Stratix® 10 BST Circuitry
7. Intel® Stratix® 10 IEEE Std. 1149.1 BST Guidelines
8. Document Revision History for the Intel® Stratix® 10 JTAG Boundary-Scan Testing User Guide
Visible to Intel only — GUID: sss1438255014442
Ixiasoft
2.2. JTAG Pins
Pin | Function | Description |
---|---|---|
TDI | Serial input pin for:
|
|
TDO | Serial output pin for:
|
|
TMS | Input pin that provides the control signal to determine the transitions of the TAP controller state machine. |
|
TCK | The clock input to the BST circuitry. | — |