Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

4.2. Intel® Stratix® 10 GX FPGA

The development board features the Intel® Stratix® 10 GX FPGA (1SG280UF50).

For the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit, there are two versions in production listed below.

Table 5.  Development Kit Versions in Production
Board Ordering Part Number (OPN) Device Ordering Part Number (OPN)
DK-SI-1SGX-L-A 1SG280LU2F50E2VG
DK-SI-1SGX-H-A 1SG280HU1F50E2VG

Intel® Stratix® 10 GX FPGA I/O Usage Summary

Table 6.  Stratix 10 GX FPGA Pin Table
Signal Name/Function I/O Count Description
Configuration
S10_JTAG_TCK/TDO/TDI/TMS 4 JTAG Configuration Pins
FPGA_MSEL[2:0] 2 Configuration input pins to set configuration scheme
FPGA_CONF_DONE 1 Configuration done pin
FPGA_nSTATUS 1 Configuration status pin
FPGA_INIT_DONE 1 Configuration pin to signify user mode
FPGAMSEL0 1 Configuration input pins to set configuration scheme and Chip select pin to EPCQL device
FPGA_nCONFIG 1 Configuration input pin to reset FPGA
FPGA_OSC_CLK_1 1 125 MHz Clock
FPGA_AS_CLK 1 Configuration Clock for AS configuration schemes
CPU_RESETn 1 Global reset signal
FPGA_CONFIG_D[31:0] 32 Configuration input pin that enables all IOs
FPGA_AS_DATA[3:0] 4 EPCQL data bus
FPGA_AVST_READY 1 SDM ready for AvST configuration scheme
FPGA_AVST_VALID 1 Data valid for AvST configuration scheme
FPGA_AVST_CLK 1 Configuration clock for AvST configuration scheme
FPGA_PR_DONE 1 Partial reconfiguration done pin
FPGA_PR_REQUEST 1 Partial reconfiguration request pin
FPGA_PR_ERROR 1 Partial reconfiguration error pin
NPERSTL, NPERSTR 4 Reset pin for PCIe HIP
FPGA_SDM10 1 SDM IO 10
FPGA_CvP_DONE 1 CvP configuration done pin
FPGA_SEU_ERR 1 SEU error indicate pin
VCC_SDA/VCC_SCL 2 SmartVID PMBus
VCC_ALERTn 1 SmartVID PMBus
Transceivers
SFP0_TX_DS 1 SFP+ 0 TX disable control Pin
SFP0_RS[1:0] 2 SFP+ 0 Rate Select Control Pin
SFP0_MOD_ABS 1 SFP+ 0 Module Absent Status Pin
SFP0_RX_LOS 1 SFP+ 0
SFP0_TX_FLT 1 SFP+ 0 Transmitter Fault Status Pin
SFP0_SCL 1 SFP+ 0 Management Data Clock
SFP0_SDA 1 SFP+ 0 Management Data I/O Bi-Directional Data
SFP1_TX_DIS 1 SFP+ 1 TX disable control pin
SFP1_RS[1:0] 2 SFP+ 1 Rate Select Control Pin
SFP1_MOD_ABS 1 SFP+ 1 Module Absent Status Pin
SFP1_RX_LOS 1 SFP+ 1
SFP1_TX_FLT 1 SFP+ 1 Transmitter Fault Status Pin
SFP1_SCL 1 SFP+ 1 Management Data Clock
SFP1_SDA 1 SFP+ 1 Management Data I/O Bi-Directional Data
CFP4_MOD_LOPWR 1 CFP4 Module Low Power Mode
CFP4_MOD_RSTn 1 CFP4 Module Reset
CFP4_GLB_ALRMN 1 CFP4 Program Alarm bits
CFP4_PRTADR[2:0] 3 CFP4 MDIO Physical Port Address
CFP4_TX_DIS 1 CFP4 Transmitter Disable
CFP4_RX_LOS 1 CFP4 Receiver loss of signal
CFP4_MOD_ABS 1 CFP4 Module Absent
CFP4_MDC 1 CFP4 Management Data Clock
CFP4_MDIO 1 CFP4 Management Data I/O Bi-Directional Data
eQSFP_modselL0 1 QSFP28 0 model select
eQSFP_resetL0 1 QSFP28 0 Module Reset
eQSFP_LPmode0 1 QSFP28 0 Module Low Power Mode
eQSFP_modprsL0 1 QSFP28 0 Module Present
eQSFP_intl0 1 QSFP28 0 Module Interrupt
eQSFP_scl0 1 QSFP28 0 Management Data Clock
eQSFP_sda0 1 QSFP28 0 Management Data I/O Bi-Directional Data
eQSFP_modselL1 1 QSFP28 1 model select
eQSFP_resetL1 1 QSFP28 1 Module Reset
eQSFP_LPmode1 1 QSFP28 1 Module Low Power Mode
eQSFP_modprsL1 1 QSFP28 1 Module Present
eQSFP_intl1 1 QSFP28 1 Module Interrupt
eQSFP_scl1 1 QSFP28 1 Management Data Clock
eQSFP_sda1 1 QSFP28 1 Management Data I/O Bi-Directional Data
FALAp/n[33:0] 68 FMC A LA bank GPIOs
FAHAp/n[23:0] 48 FMC A HA bank GPIOs
FAHBp/n[21:0] 44 FMC A HB bank GPIOs
RZQ_2M 1 RZQ pin for bank 2M
RZQ_3K 1 RZQ pin for bank 3K
EXTA_SDA1V8 1 FMC A I2C bus
EXTA_SCL1V8 1 FMC A I2C bus
FAPRSNT1V8_N 1 FMC A present indicator
FACLKBIR1V8 1 FMC A clock direction control
FBLAp/n[33:0] 68 FMC B LA bank GPIOs
EXTB_SDA1V8 1 FMC B I2C bus
EXTB_SCL1V8 1 FMC I2C bus
FBPRSTN1V8_N 1 FMC B present indicator
USB
USB_FULL 1 USB FIFO is full
USB_EMPTY 1 USB FIFO is empty
USB_RESETn 1 USB Reset
USB_OEn 1 USB Output Enable
USB_RDn 1 USB Read
USB_WRn 1 USB Write
USB_DATA[7:0] 8 USB Data Bus
USB_ADDR[1:0] 2 USB Address Bus
USB_SCL 1 USB Serial Clock
USB_SDA 1 USB Serial Data
Flash Memory
FM_D[31:0] 32 Flash Data Bus
FM_A[26:1] 26 Flash Address Bus
FLASH_WEn 1 Flash Write Enable Strobe
FLASH_CEn0 1 Flash Chip Enable
FLASH_CEn1 1 Flash Chip Enable
FLASH_OEn 1 Flash Output Enable
FLASH_RDYBSYn0 1 Flash ready or busy
FLASH_RDYBSYn1 1 Flash ready or busy
FLASH_RESETn 1 Flash reset
FLASH_CLK 1 Flash clock
FLASH_ADVn 1 Flash address valid
MAX V CPLD
MAX5_OEn 1 Output Enable
MAX5_CSn 1 Chip Select
MAX5_WEn 1 Write Enable
MAX5_CLK 1 Clock
MAX5_BEn[3:0] 4 Byte Enable
Switches, Buttons, LED
USER_LED[7:0] 8 Light Emitting Diodes
USER_PB[7:0] 8 Push Buttons
USER_DIP[6:0] 7 DIP Switches
USER_IO[9:0] 10 Input/Output
S10_UNLOCK 1 FPGA Unlock Switch
Ethernet
ENET_SGMII_TX_P/N 2 Ethernet SGMII Transmit Data
ENET_SGMII_RX_P/N 2 Ethernet SGMII Receive Data
ENET_RSTn 1 Reset
ENET_INTn 1 Interrupt
ENET_MDIO 1 Ethernet Management Data I/O
ENET_MDC 1 Ethernet Management Data Clock
   
Other Bus
SPARE[20:1] 20 Spare bus between Intel® Stratix® 10 and MAX® V
I2C_1V8_SCL 1 Intel® Stratix® 10 I2C bus
I2C_1V8_SDA 1 Intel® Stratix® 10 I2C bus
Temperature
OVERTEMPn 1 Intel® Stratix® 10 over temperature indicator
TEMP_ALERTn 1 Intel® Stratix® 10 temperature alert indicator
Global Clocks
CLK_50M_S10 1 50 MHz Global Clock Input
CLK_S10BOT_100M_p/n 2 100 MHz differential core clock for bottom banks
CLKIN_SMA_3C_p/n 2 Global Clock input from SMA
CLKOUT_SMA_3C_p/n 2 Dedicated Clock output to SMA
USB_FPGA_CLK 1 USB FPGA Clock
CLK_S10TOP_ADJ_p/n 2 Adjustable differential core clock for top banks
CLK_S10TOP_125M_p/n 2 125 MHz differential core clock for top banks
FACLKM2Cp/n0 2 FMC A clock input 0
FACLKM2Cp/n1 2 FMC A clock input 1
FBCLKM2Cp/n0 2 FMC B clock input 0
FBCLKM2Cp/n1 2 FMC B clock input 1
FACLKBIDIRp/n2 2 FMC A bidirectional clock 2
FACLKBIDIRp/n3 2 FMC A bidirectional clock 3
Transceiver Clocks
CLK_CFP4_644_p/n 2

Differential top REFCLK input to the transceiver bank 1C

CLKIN_SMA_1C_p/n 2

Differential bottom REFCLK input to the transceiver bank 1C

CLK_QSFP0_644MT_p/n 2

Differential top REFCLK input to the transceiver bank 1D

CLK_QSFP0_644MB_p/n 2

Differential bottomREFCLK input to the transceiver bank 1D

CLK_GXBL1E_614MT_p/n 2

Differential top REFCLK input to the transceiver bank 1E

CLK_GXBL1E_614MB_p/n 2

Differential bottom REFCLK input to the transceiver bank 1E

CLK_GXBL1F_625M_p/n 2

Differential top REFCLK input to the transceiver bank 1F

CLK_SFP_644M_p/n 2

Differential top REFCLK input to the transceiver bank 1K

CLK_GXBL1K_614M_p/n 2

Differential bottom REFCLK input to the transceiver bank 1K

CLK_GXBK1L_625M_p/n 2

Differential top REFCLK input to the transceiver bank 1L

FBGBTCLKM2_Cp/n0 2

Differential top REFCLK input to the transceiver bank 1M

CLKIN_SMA_1M_p/n 2

Differential bottomREFCLK input to the transceiver bank 1M

CLK_FMCB_644M_p/n 2

Differential top REFCLK input to the transceiver bank 1N

FBGBTCLKM2_Cp/n1 2

Differential bottom REFCLK input to the transceiver bank 1N

CLK_SMA_706M_p/n 2

Differential top REFCLK input to the transceiver bank 4C

CLKIN_SMA_4C_p/n 2

Differential bottomREFCLK input to the transceiver bank 4C

CLK_MXP1_706M_p/n 2

Differential top REFCLK input to the transceiver bank 4D

CLK_GXBR4D_644M_p/n 2

Differential bottom REFCLK input to the transceiver bank 4D

CLK_MXP2_706M_p/n 2

Differential top REFCLK input to the transceiver bank 4E

CLK_GXBR4E_644M_p/n 2

Differential bottom REFCLK input to the transceiver bank 4E

CLK_MXP3_706M_p/n 2

Differential top REFCLK input to the transceiver bank 4F

CLK_GXB4F_644M_p/n 2

Differential bottomREFCLK input to the transceiver bank 4F

FAGBTCLKM2_Cp/n0 2

Differential top REFCLK input to the transceiver bank 4K

CLKIN_SMA_4K_p/n 2

Differential bottom REFCLK input to the transceiver bank 4K

FAGBTCLKM2_Cp/n1 2

Differential top REFCLK input to the transceiver bank 4L

CLK_GXBR4L_644M_p/n 2

Differential bottom REFCLK input to the transceiver bank 4L

FAGBTCLKM2_Cp/n2 2

Differential top REFCLK input to the transceiver bank 4M

CLK_GXBR4M_625M_p/n 2

Differential bottomREFCLK input to the transceiver bank 4M

FAGBTCLKM2_Cp/n3 2

Differential top REFCLK input to the transceiver bank 4N

CLK_FMCA_706M_p/n 2

Differential bottomREFCLK input to the transceiver bank 4N

Level Two Title