JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683113
Date 10/14/2022
Public
Document Table of Contents

1.2.7. Design Example Files

There are two flows for the design example: simulation and synthesis.

Table 17.  Design Example Flows and Directory
Design Example Flow Directory
Simulation <your project>/ed_sim
Synthesis <your project>/ed_synth

The following tables list the important folders and files for simulation and synthesis.

Table 18.  Design Example Files for Simulation
Note: The simulation flow is only supported for System Console Control design example only. The simulation flow is not supported for Nios Control design example.
File Type File/Folder Description
Run script files /testbench/aldec/run_tb_top.tcl TCL run script for Riviera-PRO* simulator
/testbench/mentor/run_tb_top.tcl TCL run script for ModelSim* or QuestaSim* simulator
/testbench/synopsys/vcs/run_tb_top.sh Shell run script for VCS* simulator
/testbench/synopsys/vcsmx/run_tb_top.sh Shell run script for VCS* MX simulator
/testbench/xcelium/run_tb_top.sh Shell run script for Xcelium* simulator
Source files /testbench/models/altera_jesd204_ed_qsys_<data path>.qsys Top level Platform Designer system project
/testbench/models/altera_jesd204_subsystem_<data path>.qsys JESD204B subsystem Platform Designer system project
/testbench/models/ip/ IP folder containing instantiated IP modules
/testbench/models/altera_jesd204_ed_<data path>.sv Top level HDL
/testbench/models/tb_top.sv Top level testbench
/testbench/spi_mosi_oe.v Output buffer HDL
/testbench/switch_debouncer.v Switch debouncer HDL
/testbench/pattern/ Folder containing the test pattern generator and checker HDL
/testbench/transport_layer Folder containing assembler and de-assembler HDL.
Table 19.  Design Example Files for Synthesis
File Type File/Folder Description
Intel® Quartus® Prime project files altera_jesd204_ed_<data path>.qpf Intel® Quartus® Prime project file
altera_jesd204_ed_<data path>.qsf Intel® Quartus® Prime settings file
Source files altera_jesd204_ed_<data path>.sv Top level HDL
altera_jesd204_ed_<data path>.sdc Synopsys* Design Constraints (SDC) file containing all timing/placement constraints
transport_layer/ Folder containing assembler and de-assembler HDL
pattern/ Folder containing the test pattern generator and checker HDL
spi_mosi_oe.v Output buffer HDL
switch_debouncer.v Switch debouncer HDL
altera_jesd204_ed_qsys_<data path>.qsys Top level Platform Designer system project
altera_jesd204_subsystem_<data path>.qsys JESD204B subsystem Platform Designer system project