JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683113
Date 10/14/2022
Public
Document Table of Contents

1.2.5.1. Design Components

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 8. JESD204B Design Example Block Diagram
  • Platform Designer system
    • JESD204B subsystem
    • JTAG to Avalon master bridge—For System Console Control design example only
    • Nios subsystem—For Nios Control design example only
    • Parallel I/O (PIO)
    • ATX PLL
    • Core PLL
    • PLL reconfiguration module (For transceiver dynamic reconfiguration enabled mode only)
    • Serial Port Interface (SPI)—master module
  • Test pattern generator (For duplex and simplex TX data path only)
  • Test pattern checker (For duplex and simplex RX data path only)
  • Assembler—TX transport layer (For duplex and simplex TX data path only)
  • Deassembler—RX transport layer (For duplex and simplex RX data path only)