Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes

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1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes
1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes x
1.1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.1 1.2. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.0 1.3. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.1 1.4. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.0 1.5. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.1 1.6. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.0 1.7. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.0.0 1.8. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v19.2.0 1.9. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v19.1 1.10. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v18.1 1.11. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v18.0
1.1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.1 x
1.1.1. RAM: 2-PORT Intel® FPGA IP v20.4.1
1.2. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.0 x
1.2.1. RAM: 2-PORT Intel® FPGA IP v20.4.0
1.3. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.1 x
1.3.1. ROM: 1-PORT Intel® FPGA IP v20.2.1
1.4. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.0 x
1.4.1. ROM: 1-PORT Intel® FPGA IP v20.2.0 1.4.2. RAM: 2-PORT Intel® FPGA IP v20.2.0
1.5. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.1 x
1.5.1. RAM: 1-PORT Intel® FPGA IP v20.1.1 1.5.2. RAM: 4-PORT Intel® FPGA IP v20.1.1 1.5.3. ROM: 2-PORT Intel® FPGA IP v20.1.1
1.6. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.0 x
1.6.1. RAM: 1-PORT Intel® FPGA IP v20.1.0 1.6.2. RAM: 2-PORT Intel® FPGA IP v20.1.0 1.6.3. RAM: 4-PORT Intel® FPGA IP v20.1.0 1.6.4. ROM: 1-PORT Intel® FPGA IP v20.1.0 1.6.5. ROM: 2-PORT Intel® FPGA IP v20.1.0
1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes

1.4.1. ROM: 1-PORT Intel® FPGA IP v20.2.0

Table 6.  v20.2.0 2023.06.26
Quartus® Prime Version Description Impact
23.2 Error message is prompted when the following parameters are set in the parameter editor:
  • RAM_BLOCK_TYPE is set to MLAB.
  • Asynchronous clear feature for read address is enabled.
 IP upgrade is optional in Quartus® Prime Pro Edition software version 23.2.
  • IP regeneration is only required if customers have the similar design mentioned.
  • There are no changes to other existing features.
Level Two Title