Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes

Download PDF
ID 683110
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes
1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes x
1.1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.1 1.2. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.0 1.3. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.1 1.4. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.0 1.5. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.1 1.6. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.0 1.7. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.0.0 1.8. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v19.2.0 1.9. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v19.1 1.10. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v18.1 1.11. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v18.0
1.1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.1 x
1.1.1. RAM: 2-PORT Intel® FPGA IP v20.4.1
1.2. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.4.0 x
1.2.1. RAM: 2-PORT Intel® FPGA IP v20.4.0
1.3. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.1 x
1.3.1. ROM: 1-PORT Intel® FPGA IP v20.2.1
1.4. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.2.0 x
1.4.1. ROM: 1-PORT Intel® FPGA IP v20.2.0 1.4.2. RAM: 2-PORT Intel® FPGA IP v20.2.0
1.5. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.1 x
1.5.1. RAM: 1-PORT Intel® FPGA IP v20.1.1 1.5.2. RAM: 4-PORT Intel® FPGA IP v20.1.1 1.5.3. ROM: 2-PORT Intel® FPGA IP v20.1.1
1.6. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP v20.1.0 x
1.6.1. RAM: 1-PORT Intel® FPGA IP v20.1.0 1.6.2. RAM: 2-PORT Intel® FPGA IP v20.1.0 1.6.3. RAM: 4-PORT Intel® FPGA IP v20.1.0 1.6.4. ROM: 1-PORT Intel® FPGA IP v20.1.0 1.6.5. ROM: 2-PORT Intel® FPGA IP v20.1.0
1. Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT) Intel® FPGA IP Cores Release Notes

1.4.2. RAM: 2-PORT Intel® FPGA IP v20.2.0

Table 7.  v20.2.0 2021.06.29
Quartus® Prime Version Description Impact
20.3 Fixed the unconnected byteena port for MLAB RAM block type without read address registered when using the byte enable feature. The change is optional. You are required to perform IP upgrade if you have this configuration to ensure that the byteena port is correctly connected.
Table 8.  v20.2.0 2020.10.12
Quartus® Prime Version Description Impact
20.3 Removed support for the Use Stratix M512 emulation logic cell style for the LCs memory block type option for Stratix® 10 and Agilex™ 7 devices. You are required to either change to default logic cell style or switch to non-LCs memory block type.
Removed the Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. option for Stratix® 10 and Agilex™ 7 devices. You are required to perform IP upgrade if you set the option to false (default is true).
Updated the following parameter settings tab names:
  • Output 1 to Mixed Port Read-During-Write
  • Output 2 to Same Port Read-During-Write
—
Level Two Title