5G LDPC Intel® FPGA IP User Guide

ID 683107
Date 4/01/2024
Public
Document Table of Contents

3.1. Generating a 5G LDPC Intel® FPGA IP

To include the IP in a design, generate the IP in the Quartus® Prime software. Or optionally, you can generate a design example that includes the generated 5G LDPC IP, a C++ model, a MATLAB model, simulation scripts, and test data.
  1. Create a New Quartus® Prime project
  2. Open IP Catalog.
  3. Select DSP > Error Detection and Correction > 5G LDPC Intel® FPGA IP and click Add
  4. Enter a name for your IP variant and click Create.
    Figure 3. IP Variant File Name
    The name is for both the top-level RTL module and the corresponding .ip file.
    The parameter editor for this IP appears.
  5. Choose your parameters.
    You can choose Encoder or Decoder and select decoder parameters.
    Figure 4. 5G LDPC Parameter Editor
  6. For an optional design example, click Generate Example Design.
    The software creates files for MATLAB, C, or RTL simulations in the target directory. The software does not generate a hardware example.
    Figure 5. Design Example Directory Structure
  7. Click Generate HDL.
Quartus® Prime generates the RTL and the files necessary to instantiate the IP in your design and synthesize it.