5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

4.1.1. 5G LDPC Decoder Signals

Figure 11. Decoder Signals
Table 12.  Decoder Interface Signals

Signal names beginning with sink_ are in the input interface to the decoder IP; signal names beginning with source_ are in the output interface from the decoder IP (except for sink_ready and source _ready). Both interfaces comply with the Avalon® -ST specification with readyLatency=0.

Name Direction Description
clk Input Clocks the 5G LDPC decoder IP signals and internal transitions.
reset_n Input Active low, synchronous reset signal for 5G LDPC decoder. Asserting this signal for one clock cycle is sufficient to ensure the reset process initiates.
version[7:0] Output Version number.For IP version 21.1.0, version = 0x0C).
Name Direction Description
sink_valid Input Qualifies the sink_data signal. When sink_valid is not asserted, the IP stops processing input until you reassert the sink_valid signal.
sink_sop Input Marks the start of an incoming packet.
sink_eop Input Marks the end of an incoming packet.
sink_ready Output Indicates that the decoder is ready to receive data on the current clock cycle. The IP can backpressure incoming data by deasserting this signal.

The readyLatency for this signal is 0: the IP can read valid input data in the same clock cycle in which it raises this signal. Refer to the Avalon Interface Specifications for the description of this Avalon streaming interface property.

sink_data[(64*IN_WIDTH)-1:0] Input Data input. The IP processes this input only while it asserts sink_ready and you assert the sink_valid signal.

The default value of IN_WIDTH is 6.

sink_mode[11:0] Input Input block mode. The value specifies the lifting size, base graph, and code rate. Refer to Input and Output Block Mode Meaning in 5G LDPC Decoder Data Formats.

This signal must be valid for the current information block when the upstream source asserts sink_sop and sink_valid.

sink_tag[7:0] Input

Block tag. An optional tag that accompanies the block from input to output. You can use this tag to identify the correspondence of the input and output block.

This signal must be valid for the current information block when the upstream source asserts sink_sop and sink_valid.
sink_max_iter[5:0] Input Specifies the maximum number of decoding iterations. The maximum value is 63.

This signal must be valid for the current information block when the upstream source asserts sink_sop and sink_valid.

Name Direction Description
source_valid Output The IP asserts this signal when source_data holds valid data.
source_sop Output The IP asserts this signal to mark the start of a packet.
source_eop Output The IP asserts this signal to mark the end of a packet.
source_ready Input Indicates that the design downstream of the IP is ready to receive data. The design can backpressure the IP by deasserting this signal.

The readyLatency for this signal is 0: the downstream design receives data the IP core drives on source_data in the same clock cycle in which the design asserts this signal. Refer to the Avalon Interface Specifications for the description of this Avalon- streaming interface property.

source_data[383:0] Output

Data output. When the IP sends valid data on this bus, it asserts the source_valid signal. If source_ready is deasserted, the decoder holds the data constant until source_ready is asserted.

If NUM_DECODERS = 1, and MAX_LF_DECODER0 is not 384,
  • source_data[383:192] is 0 if MAX_LF_DECODER0 is 192,
  • source_data[383:128] is 0 if MAX_LF_DECODER0 is 128
  • source_data[383:96] is 0 if MAX_LF_DECODER0 is 96

Otherwise, the IP uses the full bus width.
source_mode[11:0] Output The value specifies the lifting size, base graph, and code rate. Refer to Input and Output Block Mode Meaning in 5G LDPC Decoder Data Formats.

This signal is valid when source_sop and source_valid are both asserted.

source_tag[7:0] Output

Block tag. An optional tag that goes with the block from input to output. You can use this tag to establish the correspondence of the input and output block.

This signal is valid when source_sop and source_valid are both asserted.
source_blk_K[13:0] Output Transmission block size K, in bits. K is the size of the output block from the decoder IP.

This signal is valid when source_sop and source_valid are both asserted.

source_blk_Z[8:0] Output The lifting size of the output block. For the output block, only the source_blk_Z least significant bits of source_data[383:0] are valid.

This signal is valid when source_sop and source_valid are both asserted.

source_iter[5:0] Output Actual number of decode iterations by the IP to process the current output block. The count starts at 0 and might not be an accurate count of full iterations, because the decoding process might stop at any point if the decoder meets early termination criteria. The count cannot exceed the value communicated for the current transmission block via sink_max_iter minus one.

This signal is valid when source_sop and source_valid are both asserted.

source_et_pass Output Indicates whether the current information block meets early termination criteria. 0 indicates that the block does not meet early termination criteria; 1 indicates that the block meets early termination criteria.

The decoder can also assert the signal on the last iteration.

This signal is valid when source_sop and source_valid are both asserted.

Figure 12. Example 5G LDPC Decoder Input Timing DiagramThis timing diagram illustrates an example transaction on the decoder input interface. Refer to the Avalon Interface Specifications for information about the required behavior of the ready, valid, sop, eop, and data signals on this Avalon® -ST interface.
Figure 13. Example 5G LDPC Decoder Output Timing DiagramThis timing diagram illustrates an example transaction on the decoder output interface. Refer to the Avalon Interface Specifications for information about the required behavior of the ready, valid, sop, eop, and data signals on this Avalon® -ST interface.
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