AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

I/O Standards for MIPI D-PHY Implementation

Table 1.  I/O Standards for MIPI D-PHY ImplementationThis table lists the I/O standards supported for the FPGA I/O buffer for the MIPI D-PHY implementation in high-speed or low-power RX or TX mode. The recommendation has selected such that the following I/Os can co-exist in an I/O bank depending on the FPGA device.
  • High-speed
  • Low-power
  • High-speed and low-power
Device FPGA I/O Buffer Mode Signaling Mode I/O Standard I/O Voltage Supply (V)
Input Output
Cyclone® IV , Cyclone® V, Intel® Cyclone® 10 LP, Intel® MAX® 10 RX High-speed LVDS 1 2.5 2 —
Low-power HSTL-12 1, 1.2 V LVCMOS 2.5 2, 1.2 —
TX High-speed Differential HSTL-18 3 — 1.8
Low-power 1.8 V LVCMOS 3, 2.5 V LVCMOS — 1.8, 2.5
1 The LVDS can co-exist in the same I/O bank as HSTL-12 when the FPGA is configured as input buffer in Cyclone® V devices.
2 Input buffer for LVDS and HSTL-12 I/O standards are powered by VCCPD in Cyclone® V devices.
3 The Differential HSTL-18 can co-exist in the same I/O bank as 1.8 V LVCMOS when the FPGA is configured as output buffer in Cyclone® IV, Cyclone® V, Intel® Cyclone® 10 LP, and Intel® MAX® 10 devices.
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