AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

FPGA As Transmitter: HS-TX and LP-TX Modes Simulation

In the HS-TX and LP-TX mode simulation, the FPGA acts as a MIPI D-PHY TX device. The MIPI D-PHY RX device is represented by the package parasitic components with a worst case capacitive load of 3.0 pF.

When the interface is in high-speed mode, the MIPI D-PHY RX device presents a 100 Ω differential termination in this simulation (as shown in the FPGA As Transmitter HS-TX Mode IBIS Simulation Circuit diagram). When the common-mode of the lines indicates that the interface is in low-power mode, the 100 Ω termination is switched to high Z, which is not shown in the LP-TX mode IBIS simulation circuit (as shown in the FPGA As Transmitter LP-TX Mode IBIS Simulation Circuit diagram). In this simulation, the MIPI D-PHY high-speed receiver is turned off during the low-power mode operation, thus the input differential termination is removed.

The IBIS simulation uses the buffers in different modes as follows:

  • High-speed mode
    • A differential buffer is used to transmit signals.
    • Two single-ended buffers are configured as input mode to act as tri-stated outputs.
  • Low-power mode
    • A differential buffer is configured as input mode to act as tri-stated output.
    • Two single-ended buffers are used to transmit signals.
Figure 13. FPGA As Transmitter HS-TX Mode IBIS Simulation Circuit
Figure 14. FPGA As Transmitter LP-TX Mode IBIS Simulation Circuit
Level Two Title