AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

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ID 683086
Date 6/24/2022
Public
Document Table of Contents
Document Table of Contents x
1. Transceiver Layout 2. Tile Architecture Constraints 3. PCIe Guidelines 4. Document Revision History for AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage
1. Transceiver Layout x
1.1. L-Tile and H-Tile Overview
1.1. L-Tile and H-Tile Overview x
1.1.1. PLLs 1.1.2. Transmitter Clock Network 1.1.3. GXT Clock Network 1.1.4. Calibration
1.1.1. PLLs x
1.1.1.1. ATX PLL 1.1.1.2. fPLL 1.1.1.3. CMU PLL
1.1.2. Transmitter Clock Network x
1.1.2.1. Bonded Transceiver Channels - Guidelines for VCCR_GXB and VCCT_GXB
2. Tile Architecture Constraints x
2.1. Transceiver Channel Placement 2.2. Unsupported Dynamic Reconfiguration Features 2.3. Intel® Stratix® 10 L-Tile Transceiver to H-Tile Transceiver Migration 2.4. Thermal Guidelines
2.1. Transceiver Channel Placement x
2.1.1. Possible Combinations of GX and GXT Channels 2.1.2. GX Channels 2.1.3. GXT Channels 2.1.4. Bonded Channel Placement with Data Rate Change 2.1.5. Reference Clock Guidelines for L-Tile and H-Tile 2.1.6. PLL Placement
2.1.1. Possible Combinations of GX and GXT Channels x
2.1.1.1. Possible Combinations of GX and GXT Channels in H-Tile 2.1.1.2. Possible Combinations of GX and GXT Channels in L-Tile
2.1.2. GX Channels x
2.1.2.1. Non-bonded GX Channels 2.1.2.2. Bonded GX Channels
2.1.6. PLL Placement x
2.1.6.1. ATX PLL – fPLL Spacing Requirements 2.1.6.2. ATX PLL Usage Model When Driving GXT Channels 2.1.6.3. Simplex Channel Merging 2.1.6.4. TX PLL Restrictions when Using PCIe*
3. PCIe Guidelines x
3.1. PCIe Hard IP 3.2. PHY Interface for PCIe Express (PIPE)
3.1. PCIe Hard IP x
3.1.1. Channel Placement for PCIe Hard IP 3.1.2. PLL Placement for PCIe Hard IP 3.1.3. Non-PCIe and PCIe Hard IP Channel Placement in L-Tile and H-Tile
3.2. PHY Interface for PCIe Express (PIPE) x
3.2.1. Channel Placement for PIPE 3.2.2. PLL Placement for PIPE 3.2.3. Non-PCIe and PCIe PIPE Channel Placement in H-Tile 3.2.4. Non-PCIe and PCIe PIPE Channel Placement in L-Tile
1. Transceiver Layout
2. Tile Architecture Constraints
3. PCIe Guidelines
4. Document Revision History for AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

1.1.1. PLLs

Each Intel® Stratix® 10 L-tile/H-tile transceiver bank includes the following TX Phase Locked Loops (PLLs):

  • Two Advanced Transmit (ATX) PLLs
  • Two Fractional PLLs (fPLL)
  • Two Clock Multiplier Unit (CMU) PLLs (Located in channel 1 and channel 4 of each bank)
Table 1.  Transmitter PLLs in Stratix 10 L-Tile/H-Tile Devices
PLL Type Characteristics
ATX PLL
  • Best jitter performance
  • LC tank based voltage controlled oscillator (VCO)
  • Supports fractional synthesis mode (in cascade mode only)
  • Used for both bonded and non-bonded channel configurations
Fractional PLL (fPLL)
  • Ring oscillator based VCO
  • Supports fractional synthesis mode
  • Used for both bonded and non-bonded channel configurations
Clock Multiplier Unit (CMU) PLL or Channel PLL 1
  • Ring oscillator based VCO
  • Used as an additional clock source for non-bonded applications

The total number of TX PLLs per tile is:

  • Eight ATX PLLs (2 ATX PLLs per bank * 4 banks per tile)
  • Eight fPLLs (2 fPLLs per bank * 4 banks per tile)
  • Eight CMU PLLs (2 CMU PLLs per bank * 4 banks per tile)
Figure 2. Stratix 10 PLLs and Clock Networks in Two Banks of Intel® Stratix® 10 L-Tile/H-Tile The ATX PLL, fPLL and CMU PLLs can drive the x1 clock network to support non-bonded transceivers. The ATX PLL and fPLL can drive the x6 clock network to support bonded transceivers within the bank. The x6 clock network can drive the x24 clock network in adjacent banks, allowing ATX PLLs and fPLLs to support up to 24 bonded transceiver channels. The x1, x6, and x24 clock networks are described in the Transceiver Clock Network section.
Note: For further details on CGB, refer to "PLL and Clock Networks" chapter in Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.

Section Content
ATX PLL
fPLL
CMU PLL

Related Information
1 The CMU PLL or Channel PLL of channel 1 and channel 4 can be used as a transmitter PLL or as a clock data recovery (CDR) block. The channel PLL of all other channels (0, 2, 3, and 5) can only be used as a CDR.
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