Interlaken (2nd Generation) Intel® FPGA IP Release Notes

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ID 683052
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes x
1.1. Interlaken (2nd Generation) Intel® FPGA IP v21.1.3 1.2. Interlaken (2nd Generation) Intel® FPGA IP v20.0.0 1.3. Interlaken (2nd Generation) Intel® FPGA IP v19.3.0 1.4. Interlaken (2nd Generation) Intel® FPGA IP v19.2.1 1.5. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1 Update 1 1.6. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1 1.7. Interlaken (2nd Generation) Intel® FPGA IP v18.0.1 1.8. Interlaken (2nd Generation) Intel® FPGA IP v18.0 1.9. Interlaken IP Core (2nd Generation) v17.1 1.10. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
1. Interlaken (2nd Generation) Intel® FPGA IP FPGA IP Release Notes

1.6. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP v18.1

Table 6.  Version 18.1 2018.09.10
Description Impact Notes
Renamed the document tile as Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP User Guide — —
Added VHDL simulation model and testbench support for Interlaken (2nd Generation) IP core. — —
Added the following new registers to the IP core:
  • TX_READY_XCVR
  • RX_READY_XCVR
  • ILKN_FEC_XCODER_TX_ILLEGAL_STATE
  • ILKN_FEC_XCODER_RX_ILLEGAL_STATE
— These registers are only available in Intel® Stratix® 10 E-Tile device variations.
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