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1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Retrieving SEU Statistic using Mailbox Command
4. Secure Device Manager ECC and SmartVID Errors Detection
5. Agilex™ 5 SEU Mitigation Implementation Guides
6. IP and Software References
7. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
5.6.1. Launching and Setting Up the Fault Injection Debugger
5.6.2. Configuring Your Device using a Software Object File (.sof)
5.6.3. Constraining Regions for Fault Injection
5.6.4. Injecting Errors to Predefined Safe Locations
5.6.5. Blowing Fuse Bit to Enable Injecting All Error Types
5.6.6. Injecting Errors to Random Locations
5.6.7. Injecting Errors to Specific Locations
5.6.8. Injecting Double Adjacent Errors
5.6.9. Injecting SDM ECC Errors
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6.1. Advanced SEU Detection Intel® FPGA IP References
You can set various parameter settings for the Advanced SEU Detection Intel® FPGA IP to customize its behaviors, ports, and signals.
The Quartus® Prime software generates your customized Advanced SEU Detection Intel® FPGA IP according to the parameter options that you set in the parameter editor.