Cyclone® V GT FPGA Development Kit User Guide

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ID 792833
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Kit Features 2. Getting Started 3. Software Installation 4. Development Board Setup 5. Board Update Portal 6. Board Test System 7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide A. Programming the Flash Memory Device B. Additional Information
1. Kit Features x
1.1. Hardware 1.2. Software
1.2. Software x
1.2.1. Intel® Quartus® Prime Software 1.2.2. Cyclone® V GT FPGA Development Kit Installer
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. References for Getting Started
3. Software Installation x
3.1. Installing the Intel® Quartus® Prime Subscription Edition Software 3.2. Activating Your License 3.3. Installing the Development Kit 3.4. Installing the Intel® FPGA Download Cable II Driver
4. Development Board Setup x
4.1. Setting Up the Board 4.2. Factory Default Switch and Jumper Settings 4.3. Configuring the MAX® V Device to Program EPCQ 4.4. Restoring the MAX® V CPLD to the Factory Settings 4.5. Restoring the Flash Device to the Factory Settings 4.6. Configuring the FPGA Using the Intel® Quartus® Prime Programmer
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page 5.2. Using the Board Update Portal to Write User Designs
6. Board Test System x
6.1. Preparing to Run the Board Test System 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. The Power Monitor 6.5. The Clock Control
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The DDR3x40 and DDR3x64 Tabs 6.3.6. The HSMA Tab 6.3.7. The HSMB Tab
6.3.2. The System Info Tab x
6.3.2.1. Power Tree 6.3.2.2. Power Monitor 6.3.2.3. Board Information 6.3.2.4. MAX® V Registers 6.3.2.5. JTAG Chain
6.3.3. The GPIO Tab x
6.3.3.1. Character LCD and Display 6.3.3.2. User DIP Switches 6.3.3.3. User LEDs 6.3.3.4. Push Buttons
6.3.4. The Flash Tab x
6.3.4.1. Read and Start Address 6.3.4.2. Range 6.3.4.3. Write 6.3.4.4. CFI Query 6.3.4.5. Reset 6.3.4.6. Erase 6.3.4.7. Flash Memory Table and Flash Memory Map
6.3.5. The DDR3x40 and DDR3x64 Tabs x
6.3.5.1. Start 6.3.5.2. Stop 6.3.5.3. Performance Indicators 6.3.5.4. Error Control 6.3.5.5. Number of Addresses to Write and Read
6.3.6. The HSMA Tab x
6.3.6.1. Start, Stop 6.3.6.2. XCRV, LVDS, CMOS
6.3.7. The HSMB Tab x
6.3.7.1. Start, Stop 6.3.7.2. XCRV and CMOS
6.4. The Power Monitor x
6.4.1. Power Monitor Features 6.4.2. Power Monitor Controls
6.4.2. Power Monitor Controls x
6.4.2.1. General Information 6.4.2.2. Power Information 6.4.2.3. Power Graph 6.4.2.4. Graph Settings 6.4.2.5. Reset
6.5. The Clock Control x
6.5.1. Clock Control Features 6.5.2. Clock Control Controls
6.5.2. Clock Control Controls x
6.5.2.1. Serial Port Registers 6.5.2.2. fXTAL 6.5.2.3. Target Frequency 6.5.2.4. Clear 6.5.2.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Converting Additional Files A.5. Programming Flash Memory Using the Nios® II EDS A.6. Programming Flash Memory Using the Board Update Portal
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Kit Features
2. Getting Started
3. Software Installation
4. Development Board Setup
5. Board Update Portal
6. Board Test System
7. Document Revision History for Cyclone® V GT FPGA Development Kit User Guide
A. Programming the Flash Memory Device
B. Additional Information

6.3.2.4. MAX® V Registers

The MAX® V registers control allows you to view and change the current MAX® V register values as described in the following table. Changes to the register values with the GUI take effect immediately. For example, writing a 0 to SRST resets the board.

Table 7.   MAX® V Registers
Register Name Read/Write Capability Description
System Reset (SRST) Write only Set to 0 to initiate an FPGA reconfiguration.
Page Select Register (PSR) Read/Write Determines which of the up to three (0-2) pages of flash memory to use for FPGA reconfiguration. The flash memory ships with pages 0 and 1 preconfigured.
Page Select Override (PSO) Read/Write When set to 0, the value in PSR determines the page of flash memory to use for FPGA reconfiguration. When set to 1, the value in PSS determines the page of flash memory to use for FPGA reconfiguration.
Page Select Switch (PSS) Read only

Holds the current value of the illuminated PGM LED (D2-D4) based on the following encoding:

  • 0 = PGM LED (D14) and corresponds to the flash memory page for the factory hardware design.
  • 1 = PGM LED (D13) and corresponds to the flash memory page for the user hardware 1 design.
  • 2 = PGM LED (D12) and corresponds to the flash memory page for the user hardware 2 design.
  • PSO—Sets the MAX® V PSO register. The following options are available:
    • Use PSR—Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration.
    • Use PSS—Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.
  • PSR—Sets the MAX® V PSR register. The numerical value in the list corresponds to the page of flash memory to load during FPGA reconfiguration. Refer to the MAX® V Registers table above for more information.
  • PSS—Displays the MAX® V PSS register value. Refer to MAX® V Registers table for the list of available options.
  • SRST—Resets the system and reloads the FPGA with a design from flash memory based on the other MAX® V register values. Refer to MAX® V Registers table for more information.

As the System Info tab requires that a specific design is running in the FPGA at a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the Board Test System to stop running.

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