AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board

ID 750856
Date 11/14/2022
Public

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Reference Design Requirements

Use of this reference design requires the following:

  • Installation of the Intel® Quartus® Prime Pro Edition version 22.3 with support for the Intel® Agilex® device family.
  • Connection to the Intel® Agilex® F-Series FPGA development board on the bench.
  • Download of the design example available in the following location:

    https://github.com/intel/fpga-partial-reconfig

    To download the design example:

    1. Click Clone or download.
    2. Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
    3. Navigate to the tutorials/agilex_external_pr_configuration subfolder to access the reference design.