Intel® MAX® 10 FPGA Configuration User Guide

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ID 683865
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA Configuration Overview 2. Intel® MAX® 10 FPGA Configuration Schemes and Features 3. Intel® MAX® 10 FPGA Configuration Design Guidelines 4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides 5. Dual Configuration Intel® FPGA IP Core References 6. Unique Chip ID Intel® FPGA IP Core References 7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide
2. Intel® MAX® 10 FPGA Configuration Schemes and Features x
2.1. Configuration Schemes 2.2. Configuration Features 2.3. Configuration Details
2.1. Configuration Schemes x
2.1.1. JTAG Configuration 2.1.2. Internal Configuration
2.1.1. JTAG Configuration x
2.1.1.1. JTAG Pins
2.1.2. Internal Configuration x
2.1.2.1. Internal Configuration Modes 2.1.2.2. Configuration Flash Memory 2.1.2.3. In-System Programming 2.1.2.4. Initialization Configuration Bits 2.1.2.5. Internal Configuration Time
2.1.2.2. Configuration Flash Memory x
2.1.2.2.1. Configuration Flash Memory Sectors 2.1.2.2.2. Configuration Flash Memory Programming Time
2.1.2.3. In-System Programming x
2.1.2.3.1. ISP Clamp 2.1.2.3.2. Real-Time ISP 2.1.2.3.3. ISP and Real-Time ISP Instructions
2.2. Configuration Features x
2.2.1. Remote System Upgrade 2.2.2. Configuration Design Security 2.2.3. SEU Mitigation and Configuration Error Detection 2.2.4. Configuration Data Compression
2.2.1. Remote System Upgrade x
2.2.1.1. Remote System Upgrade Flow 2.2.1.2. Remote System Upgrade Circuitry 2.2.1.3. User Watchdog Timer 2.2.1.4. Dual Configuration Intel® FPGA IP Core
2.2.1.2. Remote System Upgrade Circuitry x
2.2.1.2.1. Remote System Upgrade Circuitry Signals 2.2.1.2.2. Remote System Upgrade Circuitry Input Control 2.2.1.2.3. Remote System Upgrade Input Register 2.2.1.2.4. Remote System Upgrade Status Registers 2.2.1.2.5. Master State Machine
2.2.2. Configuration Design Security x
2.2.2.1. AES Encryption Protection 2.2.2.2. Unique Chip ID 2.2.2.3. JTAG Secure Mode 2.2.2.4. Verify Protect 2.2.2.5. JTAG Instruction Availability 2.2.2.6. Configuration Flash Memory Permissions
2.2.2.1. AES Encryption Protection x
2.2.2.1.1. Encryption and Decryption
2.2.2.2. Unique Chip ID x
2.2.2.2.1. Unique Chip ID Intel® FPGA IP Core
2.2.2.3. JTAG Secure Mode x
2.2.2.3.1. JTAG Secure Mode Instructions
2.2.2.6. Configuration Flash Memory Permissions x
2.2.2.6.1. Flash Region Access Control and Immutability
2.2.3. SEU Mitigation and Configuration Error Detection x
2.2.3.1. Configuration Error Detection 2.2.3.2. User Mode Error Detection 2.2.3.3. Error Detection Timing 2.2.3.4. Recovering from CRC Errors
2.2.3.2. User Mode Error Detection x
2.2.3.2.1. Error Detection Block 2.2.3.2.2. CHANGE_EDREG JTAG Instruction
2.2.3.3. Error Detection Timing x
2.2.3.3.1. Error Detection Frequency 2.2.3.3.2. Cyclic Redundancy Check Calculation Timing
2.3. Configuration Details x
2.3.1. Configuration Sequence 2.3.2. Intel® MAX® 10 Configuration Pins
2.3.1. Configuration Sequence x
2.3.1.1. Power-up 2.3.1.2. Configuration 2.3.1.3. Configuration Error Handling 2.3.1.4. Initialization 2.3.1.5. User Mode
2.3.1.1. Power-up x
2.3.1.1.1. POR Monitored Voltage Rails for Single-supply and Dual-supply Intel® MAX® 10 Devices 2.3.1.1.2. Monitored Power Supplies Ramp Time Requirement for Intel® MAX® 10 Devices
3. Intel® MAX® 10 FPGA Configuration Design Guidelines x
3.1. Dual-Purpose Configuration Pins 3.2. Configuring Intel® MAX® 10 Devices using JTAG Configuration 3.3. Configuring Intel® MAX® 10 Devices using Internal Configuration 3.4. Implementing ISP Clamp in Intel® Quartus® Prime Software 3.5. Accessing Remote System Upgrade through User Logic 3.6. Error Detection 3.7. Enabling Data Compression 3.8. AES Encryption 3.9. Intel® MAX® 10 JTAG Secure Design Example
3.1. Dual-Purpose Configuration Pins x
3.1.1. Guidelines: Dual-Purpose Configuration Pin 3.1.2. Enabling Dual-Purpose Pin
3.1.1. Guidelines: Dual-Purpose Configuration Pin x
3.1.1.1. JTAG Pin Sharing Behavior
3.2. Configuring Intel® MAX® 10 Devices using JTAG Configuration x
3.2.1. Auto-Generating Configuration Files for Third-Party Programming Tools Generating Third-Party Programming Files using Intel® Quartus® Prime Programmer 3.2.3. JTAG Configuration Setup 3.2.4. ICB Settings in JTAG Configuration
3.3. Configuring Intel® MAX® 10 Devices using Internal Configuration x
3.3.1. Selecting Internal Configuration Modes 3.3.2. .pof and ICB Settings 3.3.3. Programming .pof into Internal Flash
3.3.2. .pof and ICB Settings x
3.3.2.1. Auto-Generated .pof 3.3.2.2. Generating .pof using Convert Programming Files Generating Third-Party Programming Files using Intel® Quartus® Prime Programmer
3.4. Implementing ISP Clamp in Intel® Quartus® Prime Software x
3.4.1. Creating IPS File 3.4.2. Executing IPS File
3.6. Error Detection x
3.6.1. Verifying Error Detection Functionality 3.6.2. Enabling Error Detection 3.6.3. Accessing Error Detection Block Through User Logic
3.7. Enabling Data Compression x
3.7.1. Enabling Compression Before Design Compilation 3.7.2. Enabling Compression After Design Compilation
3.8. AES Encryption x
3.8.1. Generating .ekp File and Encrypt Configuration File 3.8.2. Generating .jam/.jbc/.svf file from .ekp file 3.8.3. Programming .ekp File and Encrypted POF File 3.8.4. Encryption in Internal Configuration
3.8.3. Programming .ekp File and Encrypted POF File x
3.8.3.1. Programming .ekp File and Encrypted .pof Separately 3.8.3.2. Integrate the .ekp into .pof Programming
3.9. Intel® MAX® 10 JTAG Secure Design Example x
3.9.1. Internal and External JTAG Interfaces 3.9.2. JTAG WYSIWYG Atom for JTAG Control Block Access Using Internal JTAG Interface 3.9.3. Executing LOCK and UNLOCK JTAG Instructions 3.9.4. Verifying the JTAG Secure Mode
4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides x
4.1. Unique Chip ID Intel® FPGA IP Core 4.2. Dual Configuration Intel® FPGA IP Core
4.1. Unique Chip ID Intel® FPGA IP Core x
4.1.1. Instantiating the Unique Chip ID Intel® FPGA IP Core 4.1.2. Resetting the Unique Chip ID Intel® FPGA IP Core
4.2. Dual Configuration Intel® FPGA IP Core x
4.2.1. Instantiating the Dual Configuration Intel® FPGA IP Core
5. Dual Configuration Intel® FPGA IP Core References x
5.1. Dual Configuration Intel® FPGA IP Core Avalon® Memory-Mapped Address Map 5.2. Dual Configuration Intel® FPGA IP Core Parameters
6. Unique Chip ID Intel® FPGA IP Core References x
6.1. Unique Chip ID Intel® FPGA IP Core Ports
1. Intel® MAX® 10 FPGA Configuration Overview
2. Intel® MAX® 10 FPGA Configuration Schemes and Features
3. Intel® MAX® 10 FPGA Configuration Design Guidelines
4. Intel® MAX® 10 FPGA Configuration IP Core Implementation Guides
5. Dual Configuration Intel® FPGA IP Core References
6. Unique Chip ID Intel® FPGA IP Core References
7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide

7. Document Revision History for the Intel® MAX® 10 FPGA Configuration User Guide

Document Version Changes
2023.03.27
  • Updated links.
  • Updated " Intel® Agilex™ " product family name to "Intel Agilex® 7".
2022.08.08
  • Updated rows for bits 13 and 12 in table: Remote System Upgrade Input Register for Intel® MAX® 10 Devices.
  • Updated rows for offset 1, 4, 5, and 6 in table: Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map for Intel® MAX® 10 Devices.
2022.05.26
  • Updated table: Remote System Upgrade Input Register for Intel MAX 10 Devices.
  • Updated table: Dual Configuration Intel FPGA IP Core Avalon Memory-Mapped Address Map for Intel MAX 10 Devices.
  • Updated table: Port Definitions.
  • Updated Internal Configuration Modes to note removal of the Enable CONFIG_SEL pin option.
2022.01.10
  • Added new topic—Flash Region Access Control and Immutability.
  • Updated Configuration Design Security:
    • Added a security notice.
    • Added information about region access control and immutability feature.
  • Added a security notice to AES Encryption.
  • Updated AES Encryption Protection.
  • Updated the descriptions for Figure: Connection Setup for JTAG Single-Device Configuration using Download Cable and Figure: Connection Setup for JTAG Multi-Device Configuration using Download Cable.
2021.07.02 Updated Generating .pof using Convert Programming Files to include information for the User Data in Configuration Flash Memory option.
2021.06.15
  • Updated Figure: Configuration Sequence for Intel® MAX® 10 Devices.
  • Added a note to Dual Configuration Intel® FPGA IP Core References to clarify that the Dual Configuration feature is not supported in Intel® MAX® 10 devices with Compact feature option.
2020.11.05 Updated the guidelines for JTAG pins in table Dual-Purpose Configuration Pin Guidelines for Intel MAX 10 Devices.
2020.06.30
  • Updated Table: Configuration Flash Memory Programming Time for Sectors in Intel® MAX® 10 Devices to include a footnote for 10M02.
  • Added specifications for 10M02SCU324 device in the following tables:
    • Internal Configuration Time for Intel® MAX® 10 Devices (Uncompressed .rbf)
    • Internal Configuration Time for Intel® MAX® 10 Devices (Compressed .rbf)
  • Updated Table: Cyclic Redundancy Check Calculation Time for Intel® MAX® 10 Devices to include specification for device 10M02SCU324.
  • Updated topic Generating Third-Party Programming Files using Command Line with commands to generate JAM and JBC.
2019.12.23 Updated Table: ICB Values and Descriptions for Intel MAX 10 Devices to correct the default watchdog timer value from 0x1FFF to 0xFFF.
2019.10.07 Updated the description about generating third-party programming files using command line for Generating Third-Party Programming Files using Intel® Quartus® Prime Programmer in the Configuring Intel MAX 10 Devices using JTAG Configuration and Configuring Intel MAX 10 Devices using Internal Configuration sections.
2019.06.14
  • Added guideline for JTAG pin sharing feature in Table: Dual-Purpose Configuration Pin Guidelines for Intel® MAX® 10 Devices.
  • Renamed sections to Internal and External JTAG Interfaces and JTAG WYSIWYG Atom for JTAG Control Block Access Using Internal JTAG Interface under the section Intel® MAX® 10 JTAG Secure Design Example.
  • Updated Figure: Internal and External JTAG Interface Connections to correct external JTAG pin directions, remove ports from internal JTAG block, and add labels for JTAG WYSIWYG atom, JTAG WYSIWYG interface, and external JTAG pins.
  • Added description that offset 2 bits are not one-hot and description for offset 3 on busy signal deassertion in Table: Dual Configuration Intel® FPGA IP Core Avalon® -MM Address Map for Intel® MAX® 10 Devices.
2019.04.30 Updated Table: Dual Configuration Intel® FPGA IP Core Avalon® -MM Address Map for Intel® MAX® 10 Devices to correct the offset 2 descriptions for bits 1 and 2.
2019.01.07
  • Updated the steps in following topics:
    • Enabling Dual-purpose Pin
    • Selecting Internal Configuration Modes
    • Auto-Generated .pof
    • Generating .pof using Convert Programming Files
    • Programming .pof into Internal Flash
    • Enabling Error Detection
    • Enabling Compression Before Design Compilation
    • Enabling Compression After Design Compilation
  • Updated the note in step 4b in Generating .pof using Convert Programming Files.
  • Added a note in Accessing Remote System Upgrade through User Logic.
  • Renamed the following IP core names as per Intel rebranding:
    • "Altera Dual Configuration IP core" to "Dual Configuration Intel FPGA IP"
    • "Altera Unique Chip ID IP core" to "Unique Chip ID Intel FPGA IP"
2018.10.29
  • Updated Table: ICB Values and Descriptions for Intel® MAX® 10 Devices to update the footnote for JTAG Secure feature.
  • Updated the description in User Watchdog Timer.
  • Updated the note for JTAG Secure option in Generating .pof using Convert Programming Files.
  • Updated the description of step 5 in Generating .ekp File and Encrypt Configuration File.
  • Added a note in step 4 in Enabling Dual-purpose Pin.
  • Updated Figure: Configuration Sequence for Intel® MAX® 10 Devices to add a Read ICB Settings block and a note for the Read ICB Settings block.
  • Updated Table: Dual-Purpose Configuration Pin Guidelines for Intel® MAX® 10 Devices to update the guidelines for JTAG pins.
  • Updated Figure: Connection Setup for JTAG Single-Device Configuration using Download Cable.
2018.06.01 Added 1 as valid value for n in Minimum and Maximum Error Detection Frequencies for Intel® MAX® 10 Devices table.
2018.02.12 Added steps to generate third-party programming tool files (.jbc, .jam, and .svf).
Date Version Changes
July 2017 2017.07.20
  • Updated CFM term to configuration flash memory in High-Level Overview of JTAG Configuration and Internal Configuration for MAX 10 Devices figure.
  • Added BST definition that is boundary-scan test.
June 2017 2017.06.15 Updated methods to clear the CRC error and restore the original CRC value in Verifying Error Detection Functionality.
April 2017 2017.04.06 Updated Auto-recofigure from secondary image when initial image fails (enabled by default) option to Configure device from CFM0 only reflecting user interface update.
February 2017 2017.02.21 Rebranded as Intel.
October 2016 2016.10.31
  • Updated Voltage Overshoot Prevention description.
  • Updated note in Connection Setup for JTAG Single-Device Configuration using Download Cable and Connection Setup for JTAG Multi-Device Configuration using Download Cable figures.
  • Added steps to implement ISP clamp feature.
  • Updated Configuration Flash Memory Sectors Utilization for all Intel® MAX® 10 with Analog and Flash Feature Options figure to include UFM sectors.
May 2016 2016.05.13
  • Changed instances of Standard POR to Slow POR to reflect Intel® Quartus® Prime GUI.
  • Updated tCFG to tRU_nCONFIG.
  • Corrected file type from .ekp to .pof in Step 8 of Programming .ekp File and Encrypted .pof Separately.
  • Corrected Use secondary image ISP data as default setting when available description in ICB Values and Descriptions for Intel® MAX® 10 Devices table.
  • Corrected CFM programming time.
  • Added note on JTAG pin requirements when using JTAG pin sharing.
  • Moved JTAG Pin Sharing Behavior under Guidelines: Dual-Purpose Configuration Pin.
  • Updated configuration sequence diagram by moving 'Clears configuration RAM bits from Power-up state to Reset state.
  • Corrected error detection port input and output for <crcblock_name> from input to none.
  • Added example of remote system upgrade access through user interface and port definitions.
  • Removed preliminary terms for Error Detection Frequency and Cyclic Redundancy Check Calculation Timing.
  • Added Connection Setup for JTAG Multi-Device Configuration using Download Cable diagram.
  • Updated Connection Setup for JTAG Single-Device Configuration using Download Cable diagram.
  • Added new JTAG Secure design example.
  • Edited Remote System Upgrade section title by removing in Dual Image Configuration.
  • Updated Monitored Power Supplies Ramp Time Requirement for MAX 10 Devices table.
  • Added Internal Configuration Time.
  • Removed Instant ON feature.
  • Updated User Flash Memory instances to additional UFM in Configuration Flash Memory Sectors Utilization for all MAX 10 with Analog and Flash Feature Options figure.
December 2015.12.14
  • Updated ICB setting description for Set I/O to weak pull-up prior usermode option to state the weak pull-up is enabled during configuration.
  • Removed Accessing the Remote System Upgrade Block Through User Interface.
  • Added input and output port definition for error detection WYSIWYG atom.
  • Updated the I/O pin state to be dependent on ICB bit setting during reconfiguration.
November 2015 2015.11.02
  • Removed JRunner support for JTAG configuration and link to AN 414.
  • Updated differences in supported internal configuration mode supported based on device feature options in a table.
  • Removed maximum number of compressed configuration image table do to redundancy.
  • Updated Initialization Configuration Bits setting and description to reflect Quartus Prime 15.1 update.
  • Updated Enable JTAG pin sharing and Enable nCONFIG, nSTATUS, and CONF_DONE pins to reflect Quartus II 15.1 update.
  • Added information about ISP clamp feature.
  • Updated information about steps to generate Raw Programming Data (.rpd).
  • Renamed section title from Configuration Total Flash Memory Programming Time to Configuration Flash Memory Programming Time.
  • Renamed table title from Configuration Total Flash Memory Programming Time for Sectors in Intel® MAX® 10 Devices to Configuration Flash Memory Programming Time for Sectors in Intel® MAX® 10 Devices.
  • Added note to Configuration Flash Memory Programming Time for Sectors in Intel® MAX® 10 Devices table.
  • Added information about internal JTAG interface and accessing internal JTAG block through user interface.
  • Added Intel® MAX® 10 JTAG Secure design example.
June 2015 2015.06.15
  • Added related information link to AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor in Altera Dual Configuration IP Core References and Remote System Upgrade in Dual Compressed Images.
  • Added pulse holding requirement time for RU_nRSTIMER in Remote System Upgrade Circuitry Signals for Intel® MAX® 10 Devices table.
  • Added link to Remote System Upgrade Status Register—Previous State Bit for Intel® MAX® 10 Devices table for related entries in Altera Dual Configuration IP Core Avalon-MM Address Map for Intel® MAX® 10 Devices table.
May 2015 2015.05.04
  • Rearranged and updated Configuration Setting names 'Initialization Configuration Bits for MAX 10 Devices' table.
  • Updated 'High-Level Overview of Internal Configuration for MAX 10 Devices' figure with JTAG configuration and moved the figure to 'Configuration Schemes' section.
  • Added link to corresponding description of configuration settings in 'Initialization Configuration Bits for MAX 10 Devices' table.
  • Updated the default watchdog time value from hexadecimal to decimal value in 'Initialization Configuration Bits for MAX 10 Devices' table.
  • Updated the ISP data description in 'Initialization Configuration Bits for MAX 10 Devices' table.
  • Updated 'User Watchdog Timer' by adding time-out formula.
  • Added link to 'User Watchdog Internal Circuitry Timing Specifications' in MAX 10 FPGA Device Datasheet.
  • Added footnote to indicate that JTAG secure is disabled by default and require Altera support to enable in 'Initialization Configuration Bits for MAX 10 Devices' table.
  • Updated minimum and maximum CRC calculation time for divisor 2.
  • Updated remote system upgrade flow diagram.
  • Updated 'Encryption in Internal Configuration' table by adding 'Key' terms and changed Image 1 and Image 2 to Image 0 and Image 1 respectively.
  • Added footnote to 'Encryption in Internal Configuration' to indicate auto-reconfiguration when image fails.
  • Added formula to calculate minimum and maximum CRC calculation time for other than divisor 2.
  • Added caution when JTAG Secure is turned on.
  • Added information about auto-generated .pof for certain type of internal configuration modes.
  • Added .pof and ICB setting guide through Device and Pin Options and convert programming file.
  • Added configuration RAM (CRAM) in 'Overview'
  • Editorial changes.
December 2014 2014.12.15
  • Rename BOOT_SEL pin to CONFIG_SEL pin.
  • Update Altera IP Core name from Dual Boot IP Core to Altera Dual Configuration IP Core.
  • Added information about the AES encryption key part of ICB.
  • Added encryption feature guidelines.
  • Updated ICB settings options available in 14.1 release.
  • Updated Programmer options on CFM programming available in 14.1 release.
September 2014 2014.09.22 Initial release.
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