Intel® Stratix® 10 SoC FPGA Boot User Guide

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ID 683847
Date 1/17/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
1. Introduction x
1.1. Glossary 1.2. Intel® Stratix® 10 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration - First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Intel® Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux 6.3. FPGA Partial Reconfiguration from Linux
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow
8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide

9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide

Document Version Intel® Quartus® Prime Version Changes
2024.01.17 22.4 Updated the Configuration over JTAG with HPS Boots First figure in the HPS Boots First section.
2023.09.08 22.4 Made the following change:
  • Updated information about "JTAG Configuration with HPS First" in HPS Boot First.
2023.06.22 22.4 Made the following changes:
  • Made updates to the list of "Output Files" in the HPS Boots First chapter.
2023.05.30 22.4 Updated Configuring the FPGA Fabric from U-Boot by adding the bridge disable command before the fpga load command.
2023.01.20 22.4 Made the following changes:
  • Added a note to the Configuration over AVST section.
  • Updated information in Configuration over JTAG section.
  • Added information about Partial Reconfiguration
2022.07.26 21.4 Made the following changes:
  • Added description of the REBOOT_HPS in the Reset section.
  • Added information about the maximum size of the .core.rbf and bit-stream in the Programming File Generator section.
  • Added the Intel® Stratix® 10 SoC FPGA Boot User Guide Archives section
  • Made changes to Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
    • Added the Intel® Quartus® Prime Version column
    • Converted this section from an appendix to a chapter
2021.11.10 21.1 Replaced the Supported QSPI Devices table with a link to the Intel® Supported Configuration Devices web page.
2021.05.28 21.1
  • Replaced the Creating a Configuration Bitstream for Intel® Stratix® 10 SoC FPGA section with the new Creating the Configuration Files section
  • Replaced the Generating the Linux Kernel Image section with the new Golden System Reference Design and Design Examples section
  • Renamed section Configuring the FPGA from SSBL and OS section to Configuring the FPGA Fabric from HPS Software
  • Renamed section Configuring the FPGA Using the U-Boot SSBL section to Configuring the FPGA Fabric from U-Boot
  • Renamed section Configuring the FPGA Using the Linux Operating System section to Configuring the FPGA Fabric from Linux
  • Replaced the tool: Arm* Development Studio 5* Intel® SoC FPGA Edition with Arm* Development Studio* Intel® SoC FPGA Edition
  • Removed the following sections from Debugging the HPS Boot Loader Using the Arm* Development Studio* Intel® SoC FPGA Edition :
    • Selecting the HPS Debug Interface
    • Configuring the FPGA and run the Debug FSBL
    • Creating the Debug Configuration
    • Debugging the First Stage Boot Loader (FSBL)
    • Debugging U-Boot
2020.12.04 20.2 Added a restriction to the Boot Flow Overview section that the phase 1 and phase 2 configuration files must be generated from the same Intel® Quartus® Prime Pro Edition software version.
2020.09.15 19.2
  • Added information about the differences between H- and L-tile regarding clock requirements prior to configuration in Boot Flow Overview.
  • Added information clock requirements for HPS first boot mode; and what is required for phase 1 and phase 2 in First-Stage Bootloader.
2020.06.30 19.2 Removed support for the SD/MMC configuration scheme in Intel Stratix 10 devices.
2019.12.19 19.2 Made the following changes:
  • Removed all references to EPCQ-L. This flash device is obsolete.
  • Replaced EPCQL1024 with MT25QU02G in quartus_pfg commands.
  • Removed all references to prebuilt binaries or sources inside the SoC EDS. These files are no longer included in the distribution.
  • Corrected directory path in Compiling the SRAM Object File. It should include 19.3.
  • Revised Compiling U-Boot FSBL and SSBL to get the source code from the GitHub repository.
  • Updated the version of socfpga in Compiling the Linux Kernel Image
  • Revised the debugging section.
2019.12.16 19.2 Made the following changes:
  • Changed all commands to convert programming files to use the quartus_pfg instead of quartus_cpf. The quartus_cpf command does not handle some of the advanced security features that Intel® Stratix® 10 devices support.
  • Added the following note to the Single SDM Flash topic: Due to a problem in the Intel® Quartus® Prime Pro Edition Software, if you specify the HPS boot from FPGA parameter on the FPGA Interfaces tab of the Intel® Arria® 10 Hard Processor System Intel® Arria® 10 FPGA IP GUI, this information has no effect on HPS behavior.
  • Removed statement in Creating the Raw Programming Data ( *.rpd ) File For Flash Programming topic saying that the .rpd file generated is the same size as the configuration device. This statement is not true for Intel® Stratix® 10 and later device families.
2019.07.25 19.2

Note added to explain HPS First "Phase 1 configuration" and "Phase 2 configuration" terminology in Boot Flow Overview .

2018.09.24 18.0
  • Added references to the Single QSPI Flash Boot Example.
  • Updated the filenames in accordance to the SoC EDS 18.1 version.
  • Added reference to the Micron MT25Q Support knowledge base.
  • Added the information about Testing FPGA Reconfiguration at Kernel Level.
2018.05.01 18.0 Initial release.
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