eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 5/19/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide A. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. Hardware Design Example 2.3. Simulation Design Example 2.4. Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for eCPRI Intel® FPGA IP Design Example User Guide
A. Generating and Downloading the Executable and Linking Format (.elf) Programming File

A. Generating and Downloading the Executable and Linking Format (.elf) Programming File

This section describes how to generate and download the .elf file to the board:
  1. Change directory to <design_example_dir>/synthesis/quatus.
  2. In the Intel® Quartus® Prime Pro Edition software, click Open Project and open <design_example_dir>/synthesis/quartus/epri_ed.qpf. Now select Tools > Nios II Software Build Tools for Eclipse.
    Figure 9. Nios II Software Build Tools for Eclipse
  3. The Workspace Launcher window prompt appears. In the Workspace specify the path as <design_example_dir>/synthesis/quatus to store your Eclipse project. The new Nios II - Eclipse window appears.
    Figure 10. Workspace Launcher Window
  4. In the Nios II - Eclipse window, righ-click under Project Explorer tab, and select New > Nios® II Board Support Package. The new window appears.
    Figure 11. Project Explorer Tab
  5. In the Nios II Board Support Package window:
    • In the Project name parameter, specify your desired project name.
    • In the SOPC Information File name parameter, browse to the location of <design_example_dir>/synthesis/ip_components/nios_system/nios_system.sopcinfo file. Click Finish.
    Figure 12. Nios II Board Support Package Window
  6. The newly created project appears under Project Explorer tab in Nios II - Eclipse window. Right-click under Project Explorer tab, and select Nios II > Nios II Command Shell.
    Figure 13. Project Explorer- Nios II Command Shell
  7. In the Nios II Command Shell, type the three following commands: 
    nios2-bsp hal bsp ../../nios_system/nios_system.sopcinfo
    nios2-app-generate-makefile --app-dir app --bsp-dir bsp --elf-name\ nios_system.elf --src-dir ../../../ed_fw
    make --directory=app
  8. The .elf file is generated in the following location: <design_example_dir>/synthesis/ip_components/software/<desired_project_name>/app.
  9. Type the following command in the Nios II Command Shell to download the .elf to the board:
    • For Intel® Stratix® 10:
      nios2-download -g -r -c 1 -d 2 --accept-bad-sysid app/nios_system.elf
    • For Intel® Agilex™ 7:
      nios2-download -g -r -c 1 -d 1 --accept-bad-sysid app/nios_system.elf
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