Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Creating a Partial Reconfiguration Design 2. Partial Reconfiguration Solutions IP User Guide A. Quartus® Prime Pro Edition User Guides
1. Creating a Partial Reconfiguration Design x
1.1. What's New In This Version 1.2. Partial Reconfiguration Terminology 1.3. Partial Reconfiguration Process Sequence 1.4. Internal Host Partial Reconfiguration 1.5. External Host Partial Reconfiguration 1.6. Partial Reconfiguration Design Flow 1.7. Partial Reconfiguration Design Considerations 1.8. Hierarchical Partial Reconfiguration 1.9. Partial Reconfiguration Design Timing Analysis 1.10. Partial Reconfiguration Design Simulation 1.11. Partial Reconfiguration Design Debugging 1.12. Partial Reconfiguration Security ( Stratix® 10 Designs) 1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) 1.14. Avoiding PR Programming Errors 1.15. Exporting a Version-Compatible Compilation Database for PR Designs 1.16. Creating a Partial Reconfiguration Design Revision History
1.6. Partial Reconfiguration Design Flow x
1.6.1. Step 1: Identify Partial Reconfiguration Resources 1.6.2. Step 2: Create Design Partitions 1.6.3. Step 3: Floorplan the Design 1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP 1.6.5. Step 5: Define Personas 1.6.6. Step 6: Create Revisions for Personas 1.6.7. Step 7: Compile the Base Revision and Export the Static Region 1.6.8. Step 8: Setup PR Implementation Revisions 1.6.9. Step 9: Program the FPGA Device
1.6.3. Step 3: Floorplan the Design x
1.6.3.1. Applying Floorplan Constraints Incrementally
1.6.4. Step 4: Add the Partial Reconfiguration Controller Intel® FPGA IP x
1.6.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP 1.6.4.2. Adding the Partial Reconfiguration Controller Arria® 10/Cyclone 10 FPGA IP
1.6.7. Step 7: Compile the Base Revision and Export the Static Region x
1.6.7.1. Understanding PR Logic Utilization Reports
1.6.9. Step 9: Program the FPGA Device x
1.6.9.1. Generating PR Bitstream Files 1.6.9.2. Generating PR Bitstream Files 1.6.9.3. Partial Reconfiguration Bitstream Compatibility Checking 1.6.9.4. Raw Binary Programming File Byte Sequence Transmission Examples 1.6.9.5. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.7. Partial Reconfiguration Design Considerations x
1.7.1. Partial Reconfiguration Design Guidelines 1.7.2. PR Design Timing Closure Best Practices 1.7.3. PR File Management 1.7.4. Evaluating PR Region Initial Conditions 1.7.5. Creating Wrapper Logic for PR Regions 1.7.6. Creating Freeze Logic for PR Regions 1.7.7. Resetting the PR Region Registers 1.7.8. Promoting Global Signals in a PR Region 1.7.9. Planning Clocks and other Global Routing 1.7.10. Implementing Clock Enable for On-Chip Memories
1.7.3. PR File Management x
1.7.3.1. Method 1 (Preferred): Specify Unique Entity and File Names for Each Persona 1.7.3.2. Method 2: Set QSF Assignment for a Parameterized PR Persona
1.7.8. Promoting Global Signals in a PR Region x
1.7.8.1. Viewing Row Clock Region Boundaries
1.7.10. Implementing Clock Enable for On-Chip Memories x
1.7.10.1. Clock Gating
1.8. Hierarchical Partial Reconfiguration x
1.8.1. Using Parent QDB Files from Different Compiles
1.9. Partial Reconfiguration Design Timing Analysis x
1.9.1. Running Timing Analysis on Aggregate Revisions
1.10. Partial Reconfiguration Design Simulation x
1.10.1. Partial Reconfiguration Simulation Flow 1.10.2. Simulating PR Persona Replacement
1.10.2. Simulating PR Persona Replacement x
1.10.2.1. altera_pr_persona_if Module 1.10.2.2. altera_pr_wrapper_mux_out Module 1.10.2.3. altera_pr_wrapper_mux_in Module
1.11. Partial Reconfiguration Design Debugging x
1.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer 1.11.2. Instantiating the Intel Configuration Reset Release Endpoint to Debug Logic IP
1.12. Partial Reconfiguration Security ( Stratix® 10 Designs) x
1.12.1. PR Bitstream Security Validation ( Stratix® 10 Designs) 1.12.2. PR Bitstream Authentication ( Stratix® 10 Designs) 1.12.3. PR Bitstream Encryption ( Stratix® 10 Designs)
1.13. PR Bitstream Compression and Encryption ( Arria® 10 and Cyclone® 10 GX Designs) x
1.13.1. Generating an Encrypted PR Bitstream ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Arria® 10 or Cyclone® 10 GX Designs) 1.13.3. Data Compression Comparison
1.15. Exporting a Version-Compatible Compilation Database for PR Designs x
1.15.1. Version-Compatible Database Flow for PR Designs 1.15.2. Generating a Version-Compatible Compilation Database for PR Designs
2. Partial Reconfiguration Solutions IP User Guide x
2.1. Internal and External PR Host Configurations 2.2. Partial Reconfiguration Controller Intel FPGA IP 2.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP 2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP 2.5. Partial Reconfiguration Region Controller Intel® FPGA IP 2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP 2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP 2.8. Generating and Simulating Intel® FPGA IP 2.9. Quartus® Prime Pro Edition User Guide: Partial Reconfiguration Archive 2.10. Partial Reconfiguration Solutions IP User Guide Revision History
2.2. Partial Reconfiguration Controller Intel FPGA IP x
2.2.1. Memory Map 2.2.2. Parameters 2.2.3. Ports 2.2.4. Timing Specifications 2.2.5. PR Error Recovery 2.2.6. Secure Device Manager Firmware Error Reporting
2.2.5. PR Error Recovery x
2.2.5.1. PR Error Recovery Timing Specifications
2.2.6. Secure Device Manager Firmware Error Reporting x
2.2.6.1. SDM Firmware Error Reporting Timing Specification
2.3. Partial Reconfiguration Controller Intel Arria® 10/Cyclone® 10 FPGA IP x
2.3.1. Agent Interface 2.3.2. Reconfiguration Sequence 2.3.3. Interrupt Interface 2.3.4. Parameters 2.3.5. Ports 2.3.6. Timing Specifications 2.3.7. PR Control Block and CRC Block Verilog HDL Manual Instantiation 2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation 2.3.9. PR Control Block Signals 2.3.10. Configuring an External Host for Arria® 10 or Cyclone® 10 GX Designs
2.3.4. Parameters x
2.3.4.1. Error Detection CRC Requirements
2.3.8. PR Control Block and CRC Block VHDL Manual Instantiation x
2.3.8.1. PR Control Block and CRC Block VHDL Component Declaration
2.3.9. PR Control Block Signals x
2.3.9.1. PR Control Block Signal Timing Diagrams
2.4. Partial Reconfiguration External Configuration Controller Intel FPGA IP x
2.4.1. Parameters 2.4.2. Ports 2.4.3. Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications 2.4.4. Configuring an External Host for Agilex® 7, Agilex™ 5, and Stratix® 10 Designs
2.5. Partial Reconfiguration Region Controller Intel® FPGA IP x
2.5.1. Registers 2.5.2. Parameters 2.5.3. Ports
2.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP x
2.6.1. Parameters 2.6.2. Interface Ports
2.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP x
2.7.1. Parameters 2.7.2. Ports
2.8. Generating and Simulating Intel® FPGA IP x
2.8.1. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.8.2. Running the Freeze Bridge Update script 2.8.3. IP Core Generation Output ( Quartus® Prime Pro Edition) 2.8.4. Arria® 10 and Cyclone® 10 GX PR Control Block Simulation Model 2.8.5. Generating the PR Persona Simulation Model 2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model
2.8.6. Secure Device Manager Partial Reconfiguration Simulation Model x
2.8.6.1. Monitoring the SDM 2.8.6.2. Simulating Unknown Outputs and Persona Activation 2.8.6.3. Simulation RBF Required Word Sequence
Answers to Top FAQs
1. Creating a Partial Reconfiguration Design
2. Partial Reconfiguration Solutions IP User Guide
A. Quartus® Prime Pro Edition User Guides

2.3.9. PR Control Block Signals

The following table lists the partial reconfiguration control block interface signals for the Partial Reconfiguration Controller Arria® 10 /Cyclone 10 FPGA IP:
Table 31.  PR Control Block Interface Signals
Signal Width Direction Description
pr_data [31:0] Input

Carries the configuration bitstream.
pr_done 1 Output Indicates that the PR process is complete.
pr_ready 1 Output Indicates that the control block is ready to accept PR data from the control logic.
pr_error 1 Output Indicates a partial reconfiguration error.
pr_request 1 Input Indicates that the PR process is ready to begin.
corectl 1 Input

Determines whether you are performing the partial reconfiguration internally, or through pins.

Note:
  • You can specify a configuration width of 8, 16, or 32 bits, but the interface always uses 32 pins.
  • All the inputs and outputs are asynchronous to the PR clock (clk), except data signal. data signal is synchronous to clk signal.
  • PR clock must be free-running.
  • data signal must be 0 while waiting for ready signal.

Section Content
PR Control Block Signal Timing Diagrams

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