Serial Lite III Streaming Intel® FPGA IP Core Release Notes

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Date 4/08/2024
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1. Serial Lite III Streaming Intel FPGA IP Core Release Notes
1. Serial Lite III Streaming Intel FPGA IP Core Release Notes x
1.1. Serial Lite III Streaming Intel FPGA IP Core v20.1.0 1.2. Serial Lite III Streaming Intel FPGA IP Core v20.0.2 1.3. Serial Lite III Streaming Intel FPGA IP Core v20.0.1 1.4. Serial Lite III Streaming Intel FPGA IP Core v20.0 1.5. Serial Lite III Streaming Intel FPGA IP Core v18.1 1.6. SerialLite III Streaming Intel FPGA IP Core v18.0 1.7. Intel FPGA SerialLite III Streaming IP Core v17.1 1.8. SerialLite III Streaming IP Core v17.0 1.9. SerialLite III Streaming IP Core v16.1 1.10. SerialLite III Streaming IP Core v16.0 1.11. SerialLite III Streaming IP Core v15.1 1.12. SerialLite III Streaming IP Core v15.0 1.13. SerialLite III Streaming IP Core v14.1
1. Serial Lite III Streaming Intel FPGA IP Core Release Notes

1.7. Intel FPGA SerialLite III Streaming IP Core v17.1

Table 7.  v17.1 November 2017
Description Impact
Added support for Stratix® 10 devices. New features include:
  • 28 Gbps data rate with x1 lane and 25 Gbps data rate with x2 lane .
  • Basic and full streaming mode.
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No simplex receiver mode support for more than 17.4 Gbps data rate in Stratix® 10 devices. Simplex receiver mode for greater than 17.4 Gbps data rate in Stratix® 10 is planned to be supported in future release.

In previous versions of the Intel FPGA SerialLite III Streaming IP core design example] for Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs required additional constraints. This issue has been fixed in Quartus® Prime version 17.1.

If you are migrating earlier designs with these additional constraints to Quartus® Prime version 17.1, refer to the How to I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? KDB link for more information.

SerialLite III Streaming IP core in Stratix® 10 devices does not support Riviera™-Pro 2017.02 simulator. You may use Riviera-Pro simulator prior to 2017.02 version.
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