Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

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ID 683788
Date 10/08/2019
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide 2. Developing an Intel Arria 10 SoC Custom Platform 3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide x
1.1. Intel Arria 10 SoC Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel Arria 10 SoC Development Kit Reference Platform 1.3. Intel Arria 10 SoC Development Kit Reference Platform Board Variants 1.4. Contents of the Intel Arria 10 SoC Development Kit Reference Platform 1.5. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.0 to 17.1 1.6. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.1.2 to 18.0
2. Developing an Intel Arria 10 SoC Custom Platform x
2.1. Initializing an Intel Arria 10 SoC Custom Platform 2.2. Modifying Your Intel Arria 10 SoC Custom Platform 2.3. Integrating Your Intel Arria 10 SoC Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Changing the Device Part Number 2.5. Modifying the Kernel PLL Reference Clock 2.6. Modifying the Hard Processor System 2.7. Guaranteeing Timing Closure in the Intel Arria 10 SoC Custom Platform 2.8. Generating the base.qar Post-Fit Netlist for Your Intel Arria 10 SoC FPGA Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform x
3.1. Compiling the Device Tree Blob 3.2. Compiling the Linux Kernel for the Intel Arria 10 SoC Development Kit 3.3. Compiling the OpenCL Linux Kernel Driver 3.4. Generating Full-Chip Programming File for SD Card Image 3.5. Building the SD Card Image 3.6. Known Issues
3.5. Building the SD Card Image x
3.5.1. Layout of the OpenCL Micro SD Card 3.5.2. Creating the SD Card Image 3.5.3. Guidelines on Imaging the Micro SD Card
3.5.2. Creating the SD Card Image x
3.5.2.1. Creating Partition 1 of the SD Card Image 3.5.2.2. Creating Partition 2 of the SD Card Image 3.5.2.3. Creating Partition 3 of the SD Card Image
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
2. Developing an Intel Arria 10 SoC Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

2.6. Modifying the Hard Processor System

The Intel® Arria® 10 SoC Development Kit Reference Platform uses HPS as the host system. You can modify the HPS settings in the <your_custom_platform>/hardware/<board_name>/board.qsys file. Regenerate the uboot bootloader after you change the HPS settings.

In the reference design, the HPS IP was instantiated with FPGA-to-HPS interface width set to "128-bit AXI", F2SDRAM port configuration set to "Port Configuration 3" and F2SDRAM0 and F2SDRAM2 enabled.

This instantiation was done to maximize kernel to HPS memory bandwidth. A custom IP module was instantiated between kernel memory interface and the two SDRAM ports to split kernel memory access across the ports.

Attention: You must regenerate the uboot bootloader after you change any HPS settings. For instructions on regenerating the bootloader, refer the Intel® SoC Embedded Design Suite User Guide .
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