Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core Release Notes

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ID 683755
Date 9/24/2018
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1. Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core Release Notes
1. Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core Release Notes x
1.1. Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core v18.1 1.2. Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core v18.0 1.3. Intel® Stratix® 10 Low Latency 100G Ethernet IP Core v17.1
1. Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core Release Notes

1.1. Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core v18.1

Table 1.  Version 18.1
Description Impact Notes
Added support for Auto-negotiation (AN) as defined in IEEE Standard 802.3-2015 Clause 73 and the 25G Ethernet Consortium Schedule Draft 1.6. — New feature. Use the AN/LT Options parameter to enable this feature.
Added support for Link training (LT) as defined in IEEE Standard 802.3-2015 Clauses 92 and 93 and the 25G Ethernet Consortium Schedule Draft 1.6. — New feature. Use the AN/LT Options parameters to enable this feature.
Added the dynamic control support for RS-FEC bypass capability. — —
Added support for Partial Reconfiguration. — —
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