External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.5.17. cal_debug_clk for RLDRAM 3

User calibration debug clock interface

Table 155.  Interface: cal_debug_clkInterface type: Clock Input
Port Name Direction Description
cal_debug_clk Input User clock domain