Visible to Intel only — GUID: yud1562838394485
Ixiasoft
1.1. Directory Structure
1.2. Simulation Design Example Components
1.3. Hardware Design Example Components
1.4. Generating the Design Example
1.5. Simulating the Intel Stratix 10 LL 40GbE Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Intel Stratix 10 LL 40GbE Hardware Design Example
Visible to Intel only — GUID: yud1562838394485
Ixiasoft
4. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme. If an IP core version is not listed, the user guide for the previous IP core version applies.
Intel® Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
20.3 | 19.1.0 | Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide |
20.2 | 19.1.0 | Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide |
19.3 | 19.1.0 | Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide |
17.1 S10 ES | 17.1 S10 ES | Low Latency 40-Gbps Ethernet IP Core User Guide 17.1 S10 ES |