Parallel Flash Loader Intel® FPGA IP User Guide

Download PDF
ID 683698
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.5. PFL IP Core In Embedded Systems

The PFL IP core allows processors, such as the Nios® II processor, to access the flash memory device while programming flash and configuring an FPGA.

The following figure shows how you can use the PFL IP core to program the flash memory device and to configure the FPGA with a Nios II processor. The configured Nios II processor uses the non-configuration data stored in the same flash memory device.

Figure 22. Single-Device Configuration Using the PFL With the Controller
Figure 23. Relationship Between the Four Sections in the Design Example

You must configure the Intel® FPGA with the Nios II processor when you power-up the board. You can store the Nios II processor image in the flash memory device and use the PFL IP core to configure the image to the Intel® FPGA. If you store the Nios II processor image in the same flash memory device you intend to program, do not overwrite the Nios II processor image when you program the flash memory device with other user data.

If you do not want to store the image in the flash memory device, you can store the Nios II image in a different storage device, for example an enhanced configuration (EPC) device or an erasable programmable configurable serial (EPCS) memory.

In Relationship Between the Four Sections in the Design Example figure above, the Nios II processor and the PFL IP core share the same bus line to the flash memory device. However, to avoid data contention, the processor and the IP core cannot access or program the flash memory device at the same time. To ensure that only one controller (the processor or the IP core), is accessing the flash memory device at any given time, you must tri-state all output pins from one controller to the flash memory device, while the other controller is accessing the flash memory device using the pfl_flash_access_request and pfl_flash_access_granted pins in the PFL IP core.

Table 12.  PFL Flash Access Pins and Functions
Pin Description
pfl_flash_access_request The PFL IP core drives this pin high to request access to the flash memory device.
pfl_flash_access_granted The PFL IP core enables the access to the flash memory device whenever the PFL IP core receives a high input signal at this pin.
Table 13.   pfl_flash_access_request and pfl_flash_access_granted Pins With the Nios II and PFL IP CoreTable lists the methods to use the pfl_flash_access_request and pfl_flash_access_granted pins to ensure both processors are not accessing the flash memory device at the same time.
Signal Nios II Processor PFL IP Core
High output signal at pfl_flash_access_request Tri-state all output pins to the flash memory device. Connect all input and output pins to the flash memory device when the pfl_flash_access_granted pin receives a high input.
Low output signal at pfl_flash_access_request Reconnect all pins to the flash memory device. Tri-state all output pins to the flash memory device when the pfl_flash_access_granted pin receives a low input.
Note: The Set bus pins to tri-state when not in use option for the PFL IP core disables the PFL IP core whenever the pfl_flash_access_granted pin is pulled low.
Figure 24. Nios II Processor and PFL Accessing the Flash Memory Device Sequence
Note: Intel recommends that you enable the safe state machine setting to prevent the PFL IP core from entering an undefined state. To set this option, on the Assignments menu, click Settings. In the Settings dialog box, on the Analysis and Synthesis page, click More Settings, and select safe state machine.

The Intel® CPLD and Nios II processor can each program the CFI flash memory device individually. To prevent both processors from accessing the CFI flash memory device at the same time, the flash_access_granted and flash_access_request pins of the CPLD and Nios II processor are connected together.

To use other processors or controllers in place of the Nios II processor, ensure that the pfl_flash_access_granted and pfl_flash_access_request pins of the PFL IP core connect to your processor using the method in pfl_flash_access_request and pfl_flash_access_granted Pins With the Nios II and PFL IP Core table above.

You must also specify the flash memory device read or write access time for your processor or controller. To avoid data contention when the PFL IP core is accessing the flash memory device, ensure that the output pins from your processor are tri-stated when the pfl_flash_access_request signal is high.

Related Information
Level Two Title